Kent F. Smith

A fast parallel squarer based on divide-and-conquer

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-/spl mu/m CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation.

A structured approach for VLSI circuit design

The authors review the research done on a structured, symbol-based IC design method called path programmable logic (PPL). They explain the logic partitioning strategy on which PPL is based. Compared to full-custom design methods, the PPL methods permits an order of magnitude reduction in design time. In most cases, the density of the circuits designed using the PPL method approaches or surpasses that of the practical full-custom designs. Compared to semicustom design techniques such as standard cells and gate arrays, PPL reduces the design time by a factor of three while improving the densities by a factor of two to three.<<ETX>>

Structured logic design of integrated circuits using the storage/logic array (SLA)

The Storage/Logic Array (SLA), a form of structured logic derived from PLAs, will allow development of sophisticated computer aids for VLSI design. The AND and OR planes of PLAs are folded into a single AND/OR plane. The SLA is described and comparisons with programmable logic arrays (PLAs) are made. Segmenting SLAs with arbitrary row and column breaks results in functional duality of SLA columns and allows embedded memory elements. Arbitrary SLA cell placement permits topological optimization of modules and interconnect. SLA program logic symbols map directly to IC layouts. Cell set realizations of SLAs in I2L, NMOS, and CMOS are described and compared, I2L designs are not very practical, suffering from poor fanout. Static NMOS SLA circuits provide excellent fanout, but result in high power consumption. CMOS SLA circuits use single, identical Schottky diodes for both AND and OR planes, giving dense circuits with good potential for VLSI. Programming techniques and examples are given.

A comparison of self-timed design using FPGA, CMOS, and GaAs technologies

The authors explore one approach to self-timed design and describe implementations of an example circuit in three different technologies. The simple routing chip, used as the example has been described by writing a program in OCCAM, translated into a circuit consisting of a small set of basic modules, and implemented using Actel FPGA (field-programmable gate array), CMOS, and GaAs technologies. These technologies represent a wide range of price and performance characteristics.<<ETX>>

Transforming an Ada Program Unit to Silicon and Verifying Its Behavior in an Ada Environment: A First Experiment

Although the functional behavior of this IC was tested in system, the evaluation of circuit performance should not be long in coming.

A new, precharged, low-power logic family for GaAs circuits

We present a new precharged, low-power logic family in GaAs that operates at speeds comparable to DCFL and consumes about one-fourth the power of DCFL. It uses a 2 V power supply for operation and can be used in conjunction with the widely used DCFL circuits. The logic family allows us to build complex gates in one gate delay, provides better noise margins, and is less susceptible to load capacitances than an unbuffered DCFL gate, thus making it useful for standard-cell based designs. To verify the approach, we have designed and fabricated a fully functional test chip containing a precharged full adder. >

Self-Timed Design in GaAs - Case Study of a High-Speed, Parallel Multiplier

The problems with synchronous designs at high clock fre- quencies have been well documented. This makes an asynchronous ap- proach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floating point multiplier. We first present a new architecture called the partial army of array (PAA) that is more regular than a partial tree approach while having the same latency. We then show how this architecture can be used in a self-timed implementation in the style of micropipelines. We next describe how we can design the final carry propagate adder using a new precharged logic family in GaAs that we developed as part of this project. We conclude with some genera1 observations on doing asynchronous design in GaAs. Zndex Terms- Self-timed systems, micropipelines, multipliers, GaAs, precharged circuits.

Cell matrix methodologies for integrated circuit design

Abstract A class of integrated circuit design and implementation methodologies is described. These techniques are unique in that they simultaneously model both function and interconnect using cells. Cells are designed such that cell adjacency normally implies interconnection. The absence of an interconnection is explicitly modeled as a wire break between adjacent cells. These methodologies have the potential to greatly simplify and shorten the design process since some design steps are either eliminated or merged with others. They permit near custom layout density while reducing design time over full custom design by up to thirty times and over gate array design by up to four times.

VLSI design and implementation of a real-time image segmentation processor

Image segmentation is a crucial part of machine vision applications. In this paper a system to perform real-time segmentation of images is presented. It uses a real-time segmentation VLSI chip that is based on a gradient relaxation algorithm and is designed using the Path Programmable Logic design methodology developed at the University of Utah. The system design considerations, system specifications, and an input/output format for the chip are discussed. The actual design of the chip is given that uses pipeline methodology to achieve real-time performance with a compact VLSI layout. The implementation of the segmentation system is presented and the segmentation chip and the overall system are evaluated with regard to real-time performance and segmentation results.

PPL integrated circuit design methodology

Abstract Path programmable logic (PPL) is an integrated circuit design methodology offering small layout areas, greatly reduced design time, and a high degree of technology independence. In this paper, the structure of PPL is presented, and the details of one implementation, static CMOS PPL, are shown. A conceptual model of PPL design using truth and state tables is given. A database format is presented, and the design system using this database is described. Benchmarks comparing PPL to other design methodologies show PPL compares favourably with custom design in terms of layout area while providing significant savings in design time.