Tony M. Carter

Radix-16 signed-digit division

A two-stage algorithm for fixed point, radix-16 signed-digit division is presented. The algorithm uses two limited precision radix-4 quotient digit selection stages to produce the full radix-16 quotient digit. The algorithm requires a two-digit estimate of the (initial) partial remainder and a three-digit estimate of the divisor to correctly select each successive quotient digit. The normalization of redundant signed-digit numbers requires accommodation of some fuzziness at one end of the range of numeric values that are considered normalized. A set of general equations for determining the ranges of normalized signed-digit numbers is derived. Another set of general equations for determining the precisions of estimates of the divisor and dividend are derived. These two sets of equations permit design tradeoff analyses to be made with respect to the complexity of the model division. The specific case of a two-stage radix-16 signed-digit division is presented. The staged division algorithm used can be extended to other radices as long as the signed-digital number representation used has certain properties. >

Structured logic design of integrated circuits using the storage/logic array (SLA)

The Storage/Logic Array (SLA), a form of structured logic derived from PLAs, will allow development of sophisticated computer aids for VLSI design. The AND and OR planes of PLAs are folded into a single AND/OR plane. The SLA is described and comparisons with programmable logic arrays (PLAs) are made. Segmenting SLAs with arbitrary row and column breaks results in functional duality of SLA columns and allows embedded memory elements. Arbitrary SLA cell placement permits topological optimization of modules and interconnect. SLA program logic symbols map directly to IC layouts. Cell set realizations of SLAs in I2L, NMOS, and CMOS are described and compared, I2L designs are not very practical, suffering from poor fanout. Static NMOS SLA circuits provide excellent fanout, but result in high power consumption. CMOS SLA circuits use single, identical Schottky diodes for both AND and OR planes, giving dense circuits with good potential for VLSI. Programming techniques and examples are given.

Cascade: hardware for high/variable precision arithmetic

The Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root, and computation of the greatest divisor. It is object-oriented and implements an abstract class of objects, variable precision integers. It provides a complete suite of memory management functions implemented in hardware, including a garbage collector. The Cascade hardware permits free tradeoffs of space versus time.<<ETX>>

The Structure and Operation of a Relational Database System in a Cell-Oriented Integrated Circuit Design System

An important use for a database management system is in the storage and handling of information for engineering design, particularly integrated circuit design. However, most discussions on this topic have concentrated on the layout of shapes necessary to form the various circuit elements, or connections between user-defined cells. Equally important, but often disregarded, is the necessity to support other design tools in addition to graphics for circuit layout. These include simulators and automatic layout programs that take a description of a circuit at one level and convert it to a lower level. In addition, if cells are part of a library defined and maintained by others, operations must be included to handle the maintenance of generations or versions of a cell design. These aspects of a database management system for engineering design are discussed in light of the tools being developed at the University of Utah and an extended version of System R, developed at the IBM San Jose Research Laboratory. The Utah approach emphasizes the use of previously designed and tested cells, with interconnects at fixed locations, placed on a grid. Because it is unlikely that the designers of circuits designed all (or any) of the cells used in their circuits, special database management operations are necessary to assure that a consistent, working circuit results.

Transforming an Ada Program Unit to Silicon and Verifying Its Behavior in an Ada Environment: A First Experiment

Although the functional behavior of this IC was tested in system, the evaluation of circuit performance should not be long in coming.

The set theory of arithmetic decomposition

The set theory of arithmetic decomposition is a method of designing complex addition/subtraction circuits at any radix using strictly positional, sign-local number systems. The specification of an addition circuit is simply an equation that describes the inputs and the outputs as weighted digit sets. Design is done by applying a set of rewrite rules known as decomposition operators to the equation. The order in which and weight at which each operator is applied maps directly to a physical implementation, including both multiple-level logic and connectivity. The method is readily automated, and has been used to design some higher radix arithmetic circuits. It is possible to compute the cost of a given adder before the detailed design is complete. >

Cell matrix methodologies for integrated circuit design

Abstract A class of integrated circuit design and implementation methodologies is described. These techniques are unique in that they simultaneously model both function and interconnect using cells. Cells are designed such that cell adjacency normally implies interconnection. The absence of an interconnection is explicitly modeled as a wire break between adjacent cells. These methodologies have the potential to greatly simplify and shorten the design process since some design steps are either eliminated or merged with others. They permit near custom layout density while reducing design time over full custom design by up to thirty times and over gate array design by up to four times.

Structured arithmetic tiling of integrated circuits

Robertsons Theory of Decomposition and Structured Tiling (an IC design technique) are combined in a structured arithmetic circuit design method. This method, extended by a set of inverse operators and a set of multiply operators, is used with computer-aided design tools to automate the design of arithmetic circuits.

Structured Logic Design of Integrated Circuits Using the Storage/Logic Array (SLA)

The Storage/Logic Array (SLA), a form of structured logic derived from PLAs, will allow development of sophisticated computer aids for VLSI design. The AND and OR planes of PLAs are folded into a single AND/OR plane. The SLA is described and comparisons with programmable logic arrays (PLAs) are made. Segmenting SLAs with arbitrary row and column breaks results in functional duality of SLA columns and allows embedded memory elements. Arbitrary SLA cell placement permits topological optimization of modules and interconnect. SLA program logic symbols map directly to IC layouts. Cell set realizations of SLAs in I2L, NMOS, and CMOS are described and compared, I2L designs are not very practical, suffering from poor fanout. Static NMOS SLA circuits provide excellent fanout, but result in high power consumption. CMOS SLA circuits use single, identical Schottky diodes for both AND and OR planes, giving dense circuits with good potential for VLSI. Programming techniques and examples are given.

The CMOS SLA Implementation and SLA Program Structures

The storage/logic array (SLA) is a form of structured logic which is well suited to VLSI design. The SLA concept, which was derived from the PLA, was originally conceived by Patil [3] and later elaborated upon by Patil and Welch [4]. The SLA differs from the PLA in several major respects. The SLA has both the AND and the OR planes from the PLA, but these planes are superimposed or folded on top of each other. This folding of the AND and OR planes generates a structure in which AND terms are generated on the rows of the SLA and the OR terms are generated on the columns. The single AND/OR plane of the SLA contains column wires which can serve as inputs to the SLA rows (AND plane) or as outputs from the OR plane. This functional duality of SLA columns means not only that the SLA can be arbitrarily segmented, but that inputs to and outputs from segments of the SLA can be arbitrarily interleaved.