Kentaro Shibahara

Atomic layer controlled deposition of silicon nitride with self‐limiting mechanism

Thin (2–10 nm) silicon nitride films have been grown by repetitive plasma nitridation of Si using a NH3 remote plasma and deposition of Si by a SiH2Cl2 thermal reaction. The deposition rate is self‐limited at nearly half‐molecular layer (ML) per one deposition cycle. The process window for the half‐ML/cycle of growth has been investigated with respect to the NH3 plasma power, SiH2Cl2 exposure time, and substrate temperature. The thickness fluctuation of the film over a 2 in. wafer is within measurement accuracy of the ellipsometer (± 1.9%) for the atomic layer controlled film while it is ± 8.5% for all the remote‐plasma chemical vapor deposition film.

Atomic layer controlled deposition of silicon nitride and in situ growth observation by infrared reflection absorption spectroscopy

Abstract We have previously reported that silicon nitride films can be grown by repetitive plasma nitridation of Si using a NH3 remote-plasma and deposition of Si by a SiH2Cl2 thermal reaction. For this process, the deposition rate is self-limited at nearly half-molecular-layer (ML) per one deposition cycle. In this paper, the growth mechanism of the atomic layer deposition (ALD) of silicon nitride has been investigated by in situ Fourier transform infrared reflection absorption spectroscopy (FTIR-RAS). The AFM observation showed that the surface microroughness of the ALD grown silicon nitride film on the thermal CVD Si3N4 is very large, which suggests the islands growth. On the other hand, the roughness is almost maintained after the growth on the hydrogen terminated Si and SiO2 substrates. These results are explained taking account the surface hydrogen atoms. Furthermore, in order to reduce the ion energy of the NH3 plasma, the effect of the magnetic field is investigated.

Limit of gate oxide thickness scaling in MOSFETs due to apparent threshold voltage fluctuation induced by tunnel leakage current

We report on a new roadblock which will limit the gate oxide thickness scaling of MOSFETs. It is found that statistical distribution of direct tunnel leakage current through 1.2 to 2.8 nm thick gate oxides induces significant fluctuations in the threshold voltage and transconductance when the gate oxide tunnel resistance becomes comparable to gate poly-Si resistance. By calculating the measured tunnel current based on multiple scattering theory, it is shown that the device characteristics fluctuations will be problematic when the gate oxide thickness is scaled down to less than 1 nm.

Fabrication of P-N Junction Diodes Using Homoepitaxially Grown 6H-SiC at Low Temperature by Chemical Vapor Deposition

Homoepitaxial growth on a 6H-SiC (0001)Si face was carried out successfully at 1500°C by chemical vapor deposition. This temperature is 300°C lower than typical well-known growth temperatures. The p-n junction diodes were fabricated with the grown layers and showed very good rectification. The breakdown electric field was estimated to be 2.4×106 V/cm using the characteristics of the p-n junction diodes. This value is comparable with high-temperature grown layers. The fabricated p-n junction diodes showed blue light emission in the forward-biased region.

Fundamental limit of gate oxide thickness scaling in advanced MOSFETs

The statistical distribution of the direct tunnel leakage current through the ultrathin gate oxides of MOSFETs induces significant fluctuations in the threshold voltage and the transconductance when the gate oxide tunnel resistance becomes comparable to the gate poly-Si resistance. By calculating the measured tunnel current based on multiple scattering theory, it is shown that the threshold voltage and the transconductance fluctuations will be problematic when the gate oxide thickness is scaled down to about 0.8 nm.

Metal-Oxide-Semiconductor Characteristics of Chemical Vapor Deposited Cubic-SiC

Thermal oxidation of chemical vapor deposited (CVD) cubic-SiC and fabrication of MOS diodes using a thermal oxide film were carried out. The thermal oxide was found to be SiO2 by Auger electron spectroscopic analysis. Capacitance-voltage curves of MOS diodes measured under the dark condition showed deep depletion characteristics. Inversion characteristics were observed under the illuminated condition for the first time.

High-Rate GaAs Epitaxial Lift-Off Technique for Optoelectronic Integrated Circuits

In the epitaxial lift-off (ELO) technique, where a GaAs device structure is lifted off from a GaAs substrate using selective wet etching of an AlAs release layer, the etching rate of the AlAs layer is increased by a factor of ~8 by raising the etchant temperature to 40° C and adding a surfactant and an antifoaming agent to the etching solution. The mechanism of the high-rate lift-off process is discussed based on the solubility and the diffusion coefficient of the etching product ( H2) in the etching solution. Photoluminescence measurement results show that the quality of the GaAs film is not degraded by the high-rate lift-off process. A high-rate lift-off technique for large-diameter wafers is proposed.

Plasma etching of CVD grown cubic SiC single crystals

Plasma etching of CVD grown cubic SiC single crystals with CF4+O2 mixture gas was investigated for the first time. The O2 gas composition, rf power and pressure dependence of the etching rate were clarified. The maximum etching rate was obtained with the O2 gas composition of 67%. The ratio of the etching rate between cubic SiC and Cr was found to be about 8.3, which indicates Cr as a good etching mask for cubic SiC.

High‐Speed GaAs Epitaxial Lift‐Off and Bonding with High Alignment Accuracy Using a Sapphire Plate

We report more than one order of magnitude (~18 times) enhancement in the AlAs etching rate in a GaAs epitaxial lift‐off technique compared with that at 0°C reported previously. This has been achieved by optimizing various physical parameters such as pressure and temperature, and by adding a surfactant and antifoaming agent to the HF solution. The sapphire plate on which the sample is adhered is useful in further processing. Thus, lifted‐off GaAs/AlGaAs double heterostructures exhibit good luminescence characteristics compared to the as‐grown samples.

Workfunction Tuning Using Various Impurities for Fully Silicided NiSi Gate

Workfunction tuning by the implantation of various impurities and by changing silicidation conditions was investigated for a fully silicided NiSi gate. In the case of Sb implantation, it was found that the NiSi gate workfunction was decreased by 0.34 eV from 4.60 eV, for an undoped NiSi gate, to 4.26 eV due to the lowering of the silicidation temperature. Ge, which has not been used for workfunction tuning before, induced a decrease in NiSi gate workfunction in the same way. In the case of In implantation, a decrease in accumulation capacitance in capacitance–voltage (C–V) characteristics was observed. The origin of this problem was found to be void formation at the oxide interface. The voids were also found in NiSi predoped with Sb and silicided at 450°C or lower.