Hidekazu Oda

Novel locally strained channel technique for high performance 55nm CMOS

A novel local strained channel (LSC) MOSFET has been fabricated by a stress control technique utilizing a strained poly silicon gate electrode. The residual compressive stress in arsenic (As) implanted polysilicon is induced by high temperature annealing of CVD SiO/sub 2/ cap with high tensile stress. On the other hand, boron (B) implanted poly silicon is free from stress. As a result, the only n-channel region is locally strained by the strained polysilicon electrode. The drain current of LSC nFETs is improved 15% compared to that of the conventional nFET without the degradation of pFET drain current. High performance 55nm CMOSFET is realized by simple process for LSC-structure.

Effect of channel direction for high performance SCE immune pMOSFET with less than 0.15 /spl mu/m gate length

A high performance CMOSFET with a channel along the <100> crystallographic axis has been developed. Current drivability of the pMOSFET is improved by about 15% by changing the channel direction from <110> to <100> due to an increase in hole mobility and high immunity against short channel effects (SCE). As a result, a drive current of 810 /spl mu/A//spl mu/m for nMOS and of 420 /spl mu/A//spl mu/m for pMOS with 0.14 /spl mu/m gate length has been achieved under 1 nA//spl mu/m off current at 1.8 V operation.

Novel SOI wafer engineering using low stress and high mobility CMOSFET with -channel for embedded RF/analog applications

For high performance RF/analog and logic device technology, novel SOI wafer engineering featuring <100>-channel SOI CMOSFET with high-resistivity substrate is proposed. Mobility of PMOSFET is improved about 16% by changing a channel direction from <110> to <100>. Moreover, the reduction of the drive current in narrow channel PMOSFET is suppressed. The maximum oscillation frequency (f/sub max/) for NMOSFET is improved around 7% by changing the buried oxide (BOX) thickness from 400 nm to 150 nm because the self-heating effect is suppressed, and is improved around 5% by changing the substrate resistivity from 10 /spl Omega/cm to 1000 /spl Omega/cm because the power loss is reduced. In this work, the wafer engineering which consists of 1) <100>-channel, 2) optimization of BOX, and 3) high resistivity substrate, is proposed to improve the RF performance of the CMOSFET.

Three-dimensional topography simulation model: etching and lithography

An etching model in which topography is derived by solving a modified diffusion equation is introduced. This model is simple and makes it possible to simulate three-dimensional (3-D) topography accurately and quickly. Based on this model, a 3-D topography simulator which can be applied in the development of photolithography and isotropic/anisotropic etching has been developed. With this simulator, it is possible to simulate the series processes and multilayer etching, such as contact hole and trench etching. By simulating photolithography, diffraction and standing-wave effects can be found clearly in the 3-D topography of the developed photoresist. In the case of an etching process which is restricted by diffusion, the dependence of the etch front topography on the window width of the mask is examined. >

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

We achieved 135 GHz f/sub max/ and 10.98 dB MSG at 40 GHz, which represent the world record data in CMOS published papers, by using a 70 nm body-tied partially-depleted (PD) SOI-CMOS with offset-implanted source-drain extension (SDE) and thick cobalt salicide. The suppression of V/sub th/ variations was also realized due to this structure. Dual offset-implanted SDE structure was proposed to realize high performance of both RF/analog and logic applications. We found that the optimized offset gate spacer width of the RF/analog parts is different from that of the logic parts.

Double stacked capacitor with self-aligned poly source/drain transistor (DSP) cell for megabit DRAM

A novel DRAM cell with a double stacked capacitor and a self-aligned poly source/drain transistor (DSP) cell is described. A storage capacitor is composed of two capacitors stacked in a trench. The first polysilicon acting as a storage node is also used as a self-aligned poly source/drain of the access transistor. The isolation region is formed by refilled oxide in openings between the active areas of the first polysilicon. This unique self-aligned structure results in a cell size of 5.95 µm2.

Leakage current observation on irregular local PN junctions forming the tail distribution of DRAM retention characteristics, with new test structure

The new test structure is proposed to observe the small leakage current for a large number of local PN junctions. This new structure makes it possible to catch the leaky cells corresponding to the tail distribution of the DRAM retention characteristics. It is found that the field enhanced thermionic emission is the leakage mechanism for both the leaky and conventional junctions. The leaky junctions are characterized by the small active energy of the traps in the depletion layer. Moreover, we observe the leakage characteristics corresponding to the DRAM bit with variable retention time. The kink phenomena can be observed in the leakage current while sweeping the voltage with trapping or detrapping the electrons from the traps.

SoC CMOS technology for NBTI/HCI immune I/O and analog circuits implementing surface and buried channel structures

A novel device architecture is presented, where surface channel (SC) pMOSFETs and buried channel (BC) pMOSFETs are fabricated on the same chip without extra process steps. High reliability for negative bias temperature instability (NBTI)/hot carrier injection (HCI) and low noise characteristics are realized by the BC structure for I/O and analog circuits, and high-speed and high integration are realized by the SC structure for core circuits in System-on-a-Chip (SoC).

80 nm CMOSFET technology using double offset-implanted source/drain extension and low temperature SiN process

Double offset-implanted source/drain extension and 550/spl deg/C silicon nitride deposition for sidewall and borderless contact have been applied to sub-0.1 /spl mu/m CMOS for improvement of short channel effect as well as parasitic resistance. Consequently, 830/400 /spl mu/A//spl mu/m drive current with 2.5 nm gate insulator has been achieved under 1 nA//spl mu/m off-leakage at 1.5 V operation with short channel tolerance to 80 nm gate length.

Structure design for submicron MOSFET on ultra thin SOI

In order to overcome the degradation of source-to-drain breakdown voltage (BV/sub dso/) in ultrathin SOI MOSFETs due to parasitic bipolar action, a gate overlapped LDD (lightly doped drain) structure was introduced for drain engineering. By the reduction of drain electric field and parasitic resistance at the source n/sup -/ region, the breakdown voltage was improved while keeping current drivability. The effect of channel doping level on BV/sub dso/ that affects the parasitic bipolar current gain was also investigated. Considering these two factors, guidelines for the structure design of submicron MOSFETs on ultrathin SOI are presented.<<ETX>>