Kevin Banovic

A novel radius-adjusted approach for blind adaptive equalization

A new radius-adjusted approach for blind adaptive equalization for quadrature amplitude modulation (QAM) signals is introduced. Static circular contours are defined around an estimated symbol point in a QAM signal constellation, which creates regions that can be mapped to adaptation phases. The equalizer tap update consists of a linearly weighted sum of adaptation criteria that is scaled by a variable step size. Each region corresponds to a fixed step size and weighting factor, which creates a time-varying tap update based on the equalizer output radius. Two new algorithms are proposed based on this new approach and the multimodulus algorithm (MMA). The first algorithm trades off MMA and constellation-matched errors to reduce the time-to-convergence and mean-squared error (MSE), while the second trades off MMA and decision-directed errors to achieve reliable transfer between error modes and to obtain low MSE. A method to tune the proposed algorithms is developed based on statistics of the radius. The proposed algorithms are compared with related blind algorithms, and simulation results confirm that the proposed algorithms lead to enhanced performance.

Joint MCMA and DD blind equalization algorithm with variable-step size

A variable step size technique is applied to joint Modified Constant Modulus Algorithm (MCMA) and Decision- Directed (DD) equalization algorithm to speed up convergence with respect to the original algorithm. The same technique is used with joint CMA and DD algorithm and exhibits improved performance.

A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators

This paper discusses the design and field programmable gate array (FPGA) implementation of a configurable 18-tap fractionally-spaced blind adaptive equalizer intellectual property (IP) core for quadrature amplitude modulation (QAM) signals. The design can be configured to implement the constant modulus algorithm (CMA), multimodulus algorithm (MMA), radius-adjusted modified-multimodulus algorithm (RMMA), and radius-adjusted multimodulus decision-directed algorithm (RMDA), while it can achieve channel equalization for square QAM signals up to 256-QAM. The input samples to the equalizer tapped delay line are sampled at twice the symbol rate, while the equalizer output and tap coefficients are updated at the symbol rate. This is exploited by the equalizer tap and update modules of the design, which utilize the same hardware to implement two consecutive equalizer taps per module. The IP core is implemented for the Altera Stratix II EP2S130F780C4 FPGA and targets cable demodulators. The implementation operates at a maximum symbol frequency of 8.055 MBaud, which is comparable to recent QAM equalizer designs for cable modems.

FPGA-based rapid prototyping of digital signal processing systems

This paper discusses the application of field programmable gate arrays (FPGAs) for digital signal processing (DSP). A survey of DSP design methodologies and computer-aided design (CAD) tools for FPGAs is presented, which includes methodologies for standard register-transfer-level (RTL) design, system-level design, and hardware/software (HW/SW) co-design. The application of FPGA emulation systems as a platform for rapid prototyping is addressed and future trends of FPGA-based DSP systems are suggested

Computationally-efficient methods for blind adaptive equalization

This paper proposes a new computationally-efficient method for blind equalization and presents a comprehensive review of existing computationally-efficient methods. The proposed method selectively updates the equalizer taps based on the equalizer output radius for QAM signal constellations. Signed-error, dithered signed-error, quantized-error, block, and update-decimated methods are discussed for computationally-efficient blind equalization. The proposed and discussed methods are applied to the constant modulus algorithm (CMA) and multi-modulus algorithm (MMA), and comparisons are provided.

FPGA Implementation of a Configurable Complex Blind Adaptive Equalizer

This paper discusses the design and field programmable gate array (FPGA) implementation of a complex 18- tap blind adaptive equalizer, which can be utilized in the development of quadrature amplitude modulation (QAM) based demodulators for cable modems. The design can be configured to achieve channel equalization for square QAM signals up to 256-QAM by means of the constant modulus algorithm (CMA), multimodulus algorithm (MMA), radius-adjusted modified-multimodulus algorithm (RMMA), and radius-adjusted multimodulus decision- directed algorithm (RMDA). The implementation operates at a maximum symbol frequency of 8.055 MBaud, which is comparable to recent QAM equalizer designs for cable modems.

Algorithms for Budget Management with Gate-Sizing and Other Low-Power Applications

This paper presents an overview of budget management and its application to low-power CMOS design. Budget management involves the incremental distribution of delay within a circuit without violating timing constraints. In low-power applications, the assigned budget can be used to reduce combinational circuit area and power dissipation. The zero-slack algorithm for slack assignment (ZSA) and the maximum-independent-set-based algorithm (MISA) for budget management are discussed, while a gate-sizing algorithm for low-power applications of budget management is presented. In gate-sizing algorithms, the template of a gate on a non-critical path is replaced by a smaller template, thereby, reducing its power dissipation. In addition, ultra-low power optimization techniques such as multi-threshold CMOS and transistor stacks are introduced as potential low-power applications for budget management

A sub-mW spectrum sensing architecture for portable IEEE 802.22 cognitive radio applications

A low power integrating mixer successive approximation register (SAR) prototype chip for spectrum sensing is fabricated for portable transceivers targeting IEEE 802.22 cognitive radio applications. The integrating mixer SAR combines mixing, current-domain windowing, and integration to implement the short-time Fourier transform. Integration with programmable time constant is incorporated within the mixer by utilizing binary-weighted capacitive loads, which double as the sampling capacitors of a SAR ADC. The design operates over a frequency range of 0.05–1.25GHz, consumes 0.88mW from 1.1/1.2V supplies and obtains an average dynamic range (DR) of 25.7–27.9dB.

A Sub-mW Integrating Mixer SAR Spectrum Sensor for Portable Cognitive Radio Applications

A low power mixed-signal integrating mixer successive approximation register (SAR) architecture is proposed for direct spectrum estimation in portable transceivers targeting IEEE 802.22 wireless regional area network cognitive radio applications. The integrating mixer SAR implements the short-time Fourier transform in the analog domain and digitizes its amplitude at the end of the integration period. The architecture consists of an array of folded double balanced mixers connected to a common subset of binary-weighted capacitive loads. Current domain windowing is applied in the first stage followed by mixing, integration and analog-to-digital conversion (ADC) in the second stage. Windowing sets the detection bandwidth and provides flexible low pass filtering while a load capacitor array enables integration with programmable time constant and acts as the sampling capacitors of a SAR ADC. A prototype chip is fabricated in IBM’s

A 1.55mW mixed-signal integrating mixer for direct spectrum estimation in 0.13μm CMOS

0.13\mu {\text{m}}