Esam Abdel-Raheem

Design of low-delay two-channel FIR filter banks using constrained optimization

Abstract Two approaches for the design of two-channel perfect reconstruction FIR filter banks with short reconstruction delays are presented. The approaches are based on constrained optimization. In the first approach, a low-order filter is first designed and the objective function of the filter bank is formulated as a quadratic programming problem with linear constraints. Then the Lagrange-multiplier method is used to design a higher-order filter. The method is simple, efficient, flexible, and an exact solution is obtained by solving a set of linear equations. The second approach can be used to design filters of equal as well as unequal lengths. In this approach, the design problem is formulated as a quadratic-constrained least-squares minimization problem which can be solved using standard minimization algorithms. Design examples are given to illustrate the advantages of the proposed approaches. The quality of reconstruction is considered very good and superior to those of existing methods.

High-speed area-efficient inner-product processor

In this paper, a novel technique for the design of a high-speed word-level twos complement fixed-point inner-product processor is described. The new scheme offers a highly regular structure ideally suited for VLSI implementation. A comparison in terms of speed and area between the proposed scheme and two other inner-product processors is presented. A reduction in the computation time ranging from 20% to 50% compared with other schemes has been achieved using the proposed processor, without a significant increase in the required area.

Efficient design of cosine-modulated filter banks

An iterative algorithm presented by Lim, Yang, and Koh (see IEEE Trans. Signal Processing, vol.41, p.1780-1789, 1993) is extended for the design of cosine-modulated pseudo-filter banks. The algorithm is simple, efficient, and results in savings in the amount of computation and design time. Design examples are included to illustrate the method.

A new inner-product processor for FIR filter implementation

A new fixed-point inner-product processor is presented to be used in an FIR array processor implementation. The processor enhances the speed of operation with a slight increase in area. Moreover, the new processor would improve the noise performance of the system since a double-precision word is assigned for the output without incurring extra communication overhead.

Systolic implementation of linear-phase FIR filters

A systematic method is used for mapping linear-phase FIR filter algorithms onto systolic hardware. The method is based on the z-domain characterization of the required filter and yields filter structures that are modular and pipelined. A special processor module is presented which performs an add-multiply-accumulate operation in the same time as a simple multiplier.<<ETX>>

QMF banks design and implementation perspectives

A framework for the design of two-channel quadrature mirror filter (QMF) banks is described. The design is performed using FIR (finite impulse response) as well as IIR (infinite impulse response) filters. A comparison is provided among design techniques to illustrate the advantages and disadvantages of such filters, and their implementation is considered.<<ETX>>

Design of low-delay perfect-reconstruction FIR filter banks for tree-structured subband coders

Two methods for the design of two-channel perfect reconstruction FIR filter banks with short reconstruction delays are presented. The first method is based on the Lagrange-multiplier method. The method is simple, efficient, flexible, and leads to a closed-form exact solution. The second method is based on a quadratic-constrained least-squares minimization. Design examples are given to illustrate the advantages of the proposed methods. The quality of reconstruction is considered very good and superior to those of existing methods.

EFFICIENT DECIMATOR AND INTERPOLATOR ARRAY STRUCTURES

New and efficient array processor implementations of polyphase FIR and IIR decimators and interpolators, with integer compression and expansion factors, are derived using an algebraic mapping technique. The technique is based on the time-domain representation of the algorithms. It has the merit of being suitable for describing multirate algorithms. The control signals necessary to implement the polyphase structures are explicitly identified. Different array structures are derived in which the inputs are broadcast or pipelined and outputs are pipelined or added simultaneously. Upper bounds on the input/output processing rates are provided in terms of system parameters and hardware delays. The work is extended to map decimators/interpolators with fractional compression/expansion factors onto systolic hardware structures. The new structures have the advantages of being modular, regular, hierarchical, and pipelined.

VLSI array processors for linear-phase FIR filters

Array processor implementations are obtained for linear-phase FIR filters. Three structures are reported in which the inputs are pipelined and/or broadcast and the outputs are pipelined. A novel structure is obtained in which the outputs are localized in separate processing elements. A comparison among the resulting structures is performed based on the processing rate, the latency, and the communication overhead perspectives. A new fixed-point array-multiplier design is then presented. The new processor can perform an add-multiply-accumulate operation in the same time as a simple multiplier. It increases the speed of operation without incurring extra silicon area or introducing extra latency to the system.

Weighted minimax design of fir QMF banks: Results and comparisons

An iterative method proposed by Chen and Lee, with certain modifications based on the weighted least squares (WLS) updating scheme proposed by Sunder and Ramachandran, is applied to the design of FIR quadrature mirror-image filter (QMF) banks. The method is used to design QMF banks having equiripple reconstruction error with analysis and synthesis filters having equiripple or least squares stop-band errors. The results are then compared with results obtained by other WLS methods described in the literature. The modified WLS method is simple and somewhat more efficient than existing WLS methods. The design of QMF banks satisfying prescribed specifications is also considered.