Kevin G. McCarthy

Modelling of lateral bipolar devices in a CMOS process

In spite of the emergence of CMOS technology, the well-controlled characteristics of bipolar transistors retain many advantages over those of CMOS transistors for some critical analog applications. This is the reason why special technologies have been proposed to combine both types of transistors on the same chip. An inexpensive and widely applicable approach lies in using bipolars that are realisable with existing CMOS technologies. Bipolar transistors occur as parasitic devices in CMOS and it is not necessary to use additional processing steps in their manufacture. These bipolar transistors, therefore, provide cost effective devices which are relatively simple to fabricate. The extraction of a DC parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. This paper proposes a method which involves the use of subcircuits incorporating three SPICE Gummel-Poon models. The development of this model, its implementation and the results obtained are outlined and discussed.

Design of multiple-metal stacked inductors incorporating an extended physical model

Modern analog circuits are heavily dependent on inductor performance, where the poor inductor quality factor (Q) of silicon processes leads to degradation in circuit efficacy, especially at RF and microwave frequencies. Several techniques have been proposed to enhance the Q of integrated on-chip inductors, but the most effective method of Q improvement is to lower the series resistance by increasing the inductor metal thickness. This paper presents the most cost-effective method of achieving a thick metal by using a standard 0.18-/spl mu/m multilayer BiCMOS process. An expanded physically based model for multiple-metal stacked inductors is presented, which expands on previous research to show the effects and limitations of stacking two, three, and four metal layers in a five-metal-layer process. The excellent accuracy of this geometrical model is illustrated with respect to a range of inductor designs showing that an improvement in Q of more than 50% may be achieved. Due to the increased parasitics in multilayer structures, the Q improvement is very frequency dependent, which is clearly predicted with the expanded model. The predictive capability of the model is further used to provide detailed insight into the effectiveness of a patterned ground shield for different substrate characteristics. This predictive ability will contribute greatly to first time right inductor designs and eliminate the expensive and time-consuming fabrication iterations required to fine tune other inductor models.

A physical compact model for direct tunneling from NMOS inversion layers

Abstract This paper presents a physically based, analytical, circuit simulation model for direct tunneling from NMOS inversion layers in a MOS structure. The model takes account of the effect of quantization on surface potential in the silicon, the supply of carriers for tunneling and the oxide transmission probability. The inclusion of quantum effects is based on a variational approach to the solution of the Poisson and Schrodinger equations in the silicon inversion layer [Rev Modern Phys 54 (1982) 437]. Usually the variational approach requires iterative solution of equations which is computationally prohibitive in a circuit simulation environment. In this paper, it is shown that by considering the dominant effects in weak and strong inversion, it is possible to formulate a set of equations which give all required quantities for the calculation of quantization in the inversion layer, without the requirement for iterative solution. The tunneling model is based on the concept of transparency. Improved formulae for the transparency and the escape frequency are used. Comparisons with coupled Poisson and Schrodinger simulations and with measurements are demonstrated.

MOS table models for circuit simulation

Compact MOSFET models for circuit simulation face several competing requirements, such as fast execution times, good accuracy and small memory requirements. This paper describes novel interpolation methods for accurate evaluation of MOSFET characteristics in weak, moderate, and strong inversion regions. These methods form the basis of a new table look-up model implemented in SPICE3F5. The table model provides great flexibility in adjustment of the simulation accuracy, speed, and memory consumption by providing a choice of interpolations and data tables. Application of the model to circuit simulation gives very accurate results in dc, transient, and ac analyses.

A SPICE compatible subcircuit model for lateral bipolar transistors in a CMOS process

This paper describes a SPICE compatible subcircuit model of a lateral pnp transistor, which was fabricated in a 0.6 /spl mu/m CMOS process. The extraction of a dc parameter set for the lateral device is more complicated than for a vertical device because of the presence of two parasitic vertical bipolar transistors which are formed by the emitter/collector, the base and the substrate regions. The SPICE Gummel-Poon model does not predict the substrate current accurately. This paper proposes a method which involves the use of a subcircuit incorporating three SPICE Gummel-Poon models [representing one lateral and two parasitic vertical bipolar junction transistors (BJTs)]. The development of this model, its implementation and the results obtained are outlined and discussed. This circuit model is SPICE compatible and can thus be used in commercial simulators. The model provides good agreement over a wide range of measured dc data including substrate current prediction.

A 20 MHz 200-500 mA Monolithic Buck Converter for RF Applications

In an RF system power amplifiers (PAs) typically consume the most power. This paper presents a buck converter design optimised for a wideband code division multiple access (WCDMA) PA. The design approach taken focuses on the optimization of switch sizing based on the overall power losses of the system including the output inductor losses. The converter is optimised for 20 MHz switching and output currents in the range of 200-500 mA. Experimented results are presented on the fabricated converter, with a maximum measured efficiency of 82%.

Design for reliability

Abstract The advent of the ULSI era, and the continuing decrease of the critical dimensions of MOSFETs, has raised a number of issues concerning the prediction of device reliability, and the consequences for overall product reliability. The established practice has been to assure reliability at the end of the lengthy product cycle. However, to achieve a shorter time-to-market, product reliability concerns should be addressed at the design stage (“design for reliability”). Accordingly, the design and implementation of reliability simulation tools, which give a prediction of the susceptibility of an IC design to device failure mechanisms, is becoming critical. This paper reviews some of the reliability simulation tools that are currently available to industry. The capability of the most popular of these tools is described for a number of different reliability hazards. A topical reliability simulation issue is addressed, and a statistical validation, comparing measured and simulated degraded ring oscillator data, is presented.

Capacitance and

This paper presents a method for measuring the complex permittivity of a dielectric material on a dielectric/metal stack without etching the dielectric layer. A series of circular capacitor test structures were designed and fabricated. For the first time, the unwanted capacitance Cp, which is formed by the oxide layer between the bottom metal layer and the silicon substrate, was defined and systematically investigated. The technique is shown to be suitable for characterization of a lead magnesium niobate-lead titanate (PMNT) material on the complex cross sections involved in the development of a novel high-k material. An extremely high- k of 1115 (high capacitance density of 26 fF/μm2) for a PMNT metal-insulator-metal (MIM) capacitor was achieved. In addition, low leakage current density of 2 × 10-10 A/cm2 and low loss tangent were also obtained. These results clearly showed that the PMNT MIM capacitors are very promising for both decoupling and more general RF and mixed-signal applications until the year 2020, according to the International Technology Roadmap for Semiconductors (ITRS).

S

The paper introduces the context for the emerging area of integrated power conversion. The key applications driving this trend are outlined and the principal competing technologies are presented encompassing system in package, system on chip and embedded substrate solutions. A system-in-package, 30MHz dc-dc converter using a stacked co-packaging approach is demonstrated. Its enabling key elements, including magnetics on Si technology, a power IC with a digital pulse width modulator and on-chip capacitor, and associated packaging techniques are also presented. A maximum measured efficiency of 71.7% is achieved on the stacked converter with a 30% area reduction compared to side-by-side implementation.

-Parameter Techniques for Dielectric Characterization With Application to High-

High-performance metal-insulator-metal (MIM) capacitors using novel Pb(Mg_0.33Nb_0.67)_0.65Ti_0.35O₃ (PMNT) thin films were fabricated and investigated. The dielectric properties of the PMNT capacitors were characterized at both dc and radio frequencies. A significant high-κ of 1115 (high capacitance density of 26 fF/μm²) for a PMNT MIM capacitor has been achieved. In addition, small leakage current density of 2 × 10^-10 A/cm² and low loss tangent of 0.0188 are also obtained. The results indicate that high-κ PMNT is a promising candidate material for high-performance MIM capacitors.