P. O'Sullivan

Dielectric Reliability Measurement Methods: A Review

Reliability of thin dielectric films such as silicon dioxide grown on single crystalline silicon is of great importance for integrated circuits of present and future technologies. For the characterization of the quality of dielectric films, it is essential to have measurement methods available which can give a measure of dielectric reliability in a relatively short time. Stress biases are usually highly accelerated and cause destructive dielectric breakdown. Testing for dielectric reliability has been performed for more than 30 years, and in that time many different stress methods have been established. This article reviews that most common dielectric reliability measurement methods and gives practical guidelines to the reliability engineer in the field of dielectric characterization. The examples and data shown here are mainly from MOS gate oxides. The aim of this review paper is to emphasize advantages and disadvantages of the various stress methods. Appropriate dielectric stress methods are pointed out for applications such as process development, process characterization, pocess control and screening (burn-in). A broad number of different measurement techniques are described in detail for which the set up of the measurement and its stress parameters are clarified. Suitable dielectric test structures and the determination of the correct voltage and thickness of the dielectric are discussed; they are essential to determine the electric field across the thin film. The identification of dielectric breakdown and the interpretation and significance of the measurement results are reviewed. A good understanding of the stress method and the various measured parameters is essential to draw correct conclusions for the lifetime of the dielectric at operating conditions. The commonly used, basic analysis techniques for the measurement results are illustrated. Finally, the influence of stress-induced leakage currents on the dielectric reliability characterization is discussed and other aspects relating to very thin oxides of future technologies are briefly described. The paper also includes a large bibliography of more than 250 references.

A physical compact model for direct tunneling from NMOS inversion layers

Abstract This paper presents a physically based, analytical, circuit simulation model for direct tunneling from NMOS inversion layers in a MOS structure. The model takes account of the effect of quantization on surface potential in the silicon, the supply of carriers for tunneling and the oxide transmission probability. The inclusion of quantum effects is based on a variational approach to the solution of the Poisson and Schrodinger equations in the silicon inversion layer [Rev Modern Phys 54 (1982) 437]. Usually the variational approach requires iterative solution of equations which is computationally prohibitive in a circuit simulation environment. In this paper, it is shown that by considering the dominant effects in weak and strong inversion, it is possible to formulate a set of equations which give all required quantities for the calculation of quantization in the inversion layer, without the requirement for iterative solution. The tunneling model is based on the concept of transparency. Improved formulae for the transparency and the escape frequency are used. Comparisons with coupled Poisson and Schrodinger simulations and with measurements are demonstrated.

Modeling and simulation of reliability for design

Abstract This paper provides a review of the use of simulation tools in the design process. It provides examples of applications where such tools can be effective in improving device functionality, yield, manufacturability and reliability. Topics covered are numerical process and device simulation, electromigration and stress migration simulation as well as circuit simulation and reliability modelling. Specific example of how such simulators work are provided and examples of currently available software tools are reviewed.

Design for reliability

Abstract The advent of the ULSI era, and the continuing decrease of the critical dimensions of MOSFETs, has raised a number of issues concerning the prediction of device reliability, and the consequences for overall product reliability. The established practice has been to assure reliability at the end of the lengthy product cycle. However, to achieve a shorter time-to-market, product reliability concerns should be addressed at the design stage (“design for reliability”). Accordingly, the design and implementation of reliability simulation tools, which give a prediction of the susceptibility of an IC design to device failure mechanisms, is becoming critical. This paper reviews some of the reliability simulation tools that are currently available to industry. The capability of the most popular of these tools is described for a number of different reliability hazards. A topical reliability simulation issue is addressed, and a statistical validation, comparing measured and simulated degraded ring oscillator data, is presented.

Extraction of coupling ratios for Fowler–Nordheim programming conditions

Abstract An analysis of extraction methodologies for the coupling ratios in non-volatile memories using numerical simulation is presented. The floating gate voltage of a non-volatile memory (NVM) cell cannot be accessed directly from measurements but can be derived using numerical simulation techniques. In this paper, various coupling ratio methodologies from literature are investigated using numerical simulation techniques and guidelines on improving the application of these methods to NVM cells are outlined. Measurements are performed which validate the increased accuracy of the methods and some of the improved methodologies are recommended for coupling ratio extraction in the Fowler–Nordheim regime. This work demonstrates the role of numerical simulation in supplementing the electrical characterisation of NVM cells.

Correlation of SiO2 lifetimes from constant and ramped voltage measurements

This paper investigates constant voltage stress (CVS) and ramped voltage stress (RVS) for thermally grown oxides on single crystal and on polycrystalline silicon. CVS is a standard stress for the measurement and prediction of oxide lifetimes. However, RVS has the advantage over CVS of recording the breakdown properties in a very fast time and is, therefore, widely used in industry. The aim of this work is the assessment of a correlation between times to breakdown of RVS and CVS. Times to breakdown of RVS and CVS are compared directly and it has been found that they do not correlate with a simple classical model. An anomaly is reported for thick oxides grown on polycrystalline silicon: greater breakdown voltages are recorded for slow ramps than for fast ramps. It is shown that the times to breakdown which are estimated from RVS are longer than times to breakdown of CVS. The increase in times is dependent on the oxide thickness. This is verified with CVS measurements on pre-stressed oxides. In contradiction to the literature, results from pre-stressed oxides were found to have greater time to breakdown and charge to breakdown values than data of virgin oxides. The results of this work give evidence that the time to breakdown and the injected charge to breakdown of the voltage stress measurements are strongly influenced by charge trapping effects in the oxide layer. Longer times to breakdown resulting from a RVS have to be taken into account when lifetimes at use conditions are predicted from RVS results. If this is not considered oxide lifetimes at operating voltage will be overestimated.

Assessing MOS gate oxide reliability on wafer level with ramped/constant voltage and current stress

In this study time to breakdown distributions are compared for MOS gate oxides which were stressed with a constant voltage (or current) stress or a pre-stressing voltage (or current) ramp followed by a constant voltage (or current) stress. Results show clearly that a pre-stress can increase time to breakdown. This increase is discussed and it is shown that it is dependent on oxide thickness, pre-stressing ramp rate and the processing conditions. The current-time (or voltage-time) characteristics of the constant stress are investigated and it is observed that charge trapping in the oxide is the reason for the time to breakdown increase. The pre-stressed oxide clearly shows a different initial charge trapping characteristic than the non prestressed oxide. The measurement results are discussed and it is demonstrated that the common understanding of oxide breakdown cannot explain the observed results. Therefore, a new parameter is proposed which is related to oxide degradation and breakdown and which has to be considered in combined ramped/constant stress measurements.

Correlation of lifetimes from CVS and RVS using the 1/E-model for thermally grown oxides on polysilicon

Accelerated stress measurements such as constant voltage stress (CVS) and ramped voltage stress (RVS) are commonly used in industry for the evaluation of oxide lifetimes. The main advantage of RVS over CVS is the short measurement time. Therefore, RVS is widely used, especially, in short dielectric screens and, lifetimes are extrapolated from the RVS measurement results. For this lifetime extrapolation a correlation between RVS data and CVS lifetimes is assumed. This correlation between CVS and RVS results is investigated for six oxides which had been thermally grown from polysilicon. CVS and RVS measurements were performed over a wide range of bias conditions and the measurement results were directly compared. This comparison showed that RVS increases oxide lifetimes. The current-time characteristics were studied in order to find the cause of the increased RVS lifetimes. They indicated lower currents for RVS than for CVS at equal bias voltage levels. Further measurements were carried out to study the effect of a RVS prior to CVS. Findings from these measurements with pre-stressed oxides confirmed the RVS lifetime increase which had been seen earlier. The increase in RVS lifetimes is critical for the prediction of oxide lifetimes at operating voltage. This increase has to be taken into account when lifetimes are predicted from RVS results. If it is not oxide lifetimes will be overestimated.

Evaluation of the lifetime and failure probability for inter-poly oxides from RVS measurements

Abstract In this paper a practical characterization methodology for inter-poly oxides is described. Three different inter-poly oxides were tested, characterized and compared. The test included Constant Voltage Stress (CVS) and Ramped Voltage Stress (RVS) measurements on small area capacitors and only RVS on large area capacitors. It is confirmed that the 1/E Berkeley model is suitable for inter-poly oxide characterization. A method for the prediction of the failure probability from RVS data of large area capacitors at operating conditions is demonstrated on the basis of the 1/E model for the comparison of the inter-poly oxides.

Direct BSIM3v3 parameter extraction for hot-carrier reliability simulation of N-channel LDD MOSFETs

A novel direct parameter extraction strategy for the BSIM3v3 MOSFET model, and its application to hot-carrier reliability simulation, is presented in this paper. The use of direct extraction procedures allows a very fast extraction of circuit reliability parameters, with a minimum of measurements, and produces physically relevant parameters. The extraction routines presented are based on the device equations of BSIM3vS, and the use of a direct scheme over an optimised scheme makes the extraction routines repeatable over a wide range of experimental conditions. The more common commercial reliability simulators available in the industrial market generate predicted parameter sets after selected durations of device operation by interpolation (or extrapolation) between measured parameter sets extracted at intervals, during a constant-bias stress. The work presented here suggests that confidence in the predicted circuit performance is dependent on very careful choice of both the parameter sets supplied to the reliability simulator, and the applied stressing conditions.