Kevin Marquet

PinaVM: a systemC front-end based on an executable intermediate representation

SystemC is the de facto standard for high-level modeling embedded systems. It allows system design at various levels of abstractions, provides typical object-orientation features and incorporates timing and concurrency concepts. A SystemC program is typically processed by a SystemC front-end in order to verify, debug and/or optimize the architecture. Designing a SystemC front-end is a difficult task and existing approaches suffer from limitations. In this paper, we present a new approach that addresses most of these limitations. We detail this approach, based on an executable intermediate representation. We introduce PinaVM, a new, open-source SystemC front-end and implementation of our contributions. We give experimental results on this tool

Software defined radio architecture survey for cognitive testbeds

In this paper we present a survey of existing prototypes dedicated to software defined radio. We propose a classification related to the architectural organization of the prototypes and provide some conclusions about the most promising architectures. This study should be useful for cognitive radio testbed designers who have to choose between many possible computing platforms. We also introduce a new cognitive radio testbed currently under construction and explain how this study have influenced the test-bed designers choices.

The GLUON family: a lightweight hash function family based on FCSRs

Since the beginning of the SHA3 competition, the cryptographic community has seen the emergence of a new kind of primitives: the lightweight cryptographic hash functions. At the time writing this article, two representatives of this category have been published: Quark [7] and PHOTON [18] designed to match RFID constraints. In this paper, we propose a third representative of this category which is called GLUON. It is based on the sponge construction model [11] as Quark and PHOTON and inspired by two stream ciphers F-FCSR-v3 [4] and X-FCSR-v2 [10]. From the generic definition of our lightweight hash function, we derive three different instances according to the required security level that must be reached. For example, our lightest instance (GLUON-128/8) dedicated to 64-bit security level fits in 2071 gate-equivalents which stays competitive when compared with the parallel implementation of U-Quark. The software performances are good for GLUON-224/32, our heaviest instance.

A compilation flow for parametric dataflow: programming model, scheduling, and application to heterogeneous MPSoC

Efficient programming of signal processing applications on embedded systems is a complex problem. High level models such as Synchronous dataflow (SDF) have been privileged candidates for dealing with this complexity. These models permit to express inherent application parallelism, as well as analysis for both verification and optimization. Parametric dataflow models aim at providing sufficient dynamicity to model new applications, while at the same time maintaining the high level of analyzability needed for efficient real life implementations. This paper presents a new compilation flow that targets parametric dataflows. Built on the LLVM compiler infrastructure, it offers an actor based C++ programming model to describe parametric graphs, a compilation front-end providing graph analysis features, and a retargetable back-end to map the application on real hardware. This paper gives an overview of this flow, with a specific focus on scheduling. The crucial gap between dataflow models and real hardware on which actor firing is not atomic, as well as the consequences on FIFOs sizing and execution pipelining are taken into account. The experimental results illustrate our compilation flow applied to compilation of 3GPP LTE-Advanced demodulation on a heterogeneous MPSoC with distributed scheduling features. This achieves performances similar to time-consuming hand made optimizations.

A DSL approach for object memory management of small devices

Small devices have a specific hardware configuration. In particular, they usually include several types of memories (typically ROM, internal and external RAM, Flash memory) different in quantities and properties. We propose an object memory management where the placement of an object in a given generation is based on different properties. This approach is supported by a domain specific language allowing to write powerful and flexible placement policies. These placement policies completely describe the placement, in the different memories, of the objects handled by the virtual machine.

Survey and benchmark of lightweight block ciphers for MSP430 16-bit microcontroller

For security applications in wireless sensor networks WSNs, choosing best algorithms in terms of energy-efficiency and of small memory requirements is a real challenge because the sensor networks are composed of low-power entities. In some previous works, 12 block-ciphers have been benchmarked on an ATMEL AVR ATtiny45 8-bit microcontroller and the best candidates to use in the context of small embedded platforms have been deduced. This article proposes to study on the TI 16-bit microcontroller MSP430 most of the recent lightweight block cipher proposals as well as some conventional block ciphers. First, we describe the design of the chosen block ciphers with a security and an implementation summary and we then present some implementation tests performed on our dedicated platform. Copyright

Incremental checkpointing of program state to NVRAM for transiently-powered systems

As technology improves, it becomes possible to design autonomous, energy-harvesting networked embedded systems, a key building block for the Internet of Things. However, running from harvested energy means frequent and unpredictable power failures. Programming such Transiently Powered Computers will remain an arduous task for the software developer, unless some OS support abstracts energy management away from application design. Various approaches were proposed to address this problem. We focus on checkpointing, i.e. saving and restoring program state to and from non-volatile memory. In this paper, we propose an incremental checkpointing scheme which aims at minimizing the amount of data written to non-volatile memory, while keeping the execution overhead as low as possible.

Peripheral state persistence for transiently-powered systems

Recently has emerged the concept of transiently-powered systems: tiny battery-less embedded systems which harvest energy from their environment. To retain information despite frequent and unpredictable power failures, a transiently-powered system can use non-volatile memory to store checkpoints of program state. However current checkpointing techniques only consider the state of computation (processor, memory) and disregard peripheral state completely. This paper presents a software framework that allows for the use of non-trivial peripherals such as analog-to-digital converters, serial interfaces or radio devices, in transiently-powered systems.

numap: A portable library for low-level memory profiling

The memory subsystem of modern multi-core architectures is becoming more and more complex with the increasing number of cores integrated in a single computer system. This complexity leads to profiling needs to let software developers understand how programs use the memory subsystem. Modern processors come with hardware profiling features to help building tools for these profiling needs. Regarding memory profiling, many processors provide means to monitor memory traffic and to sample read and write memory accesses. Unfortunately, these hardware profiling mechanisms are often very complex to use and are specific to each micro-architecture. In this work, we present numap, a library dedicated to the profiling of the memory sub-system of modern multi-core architectures. numap is portable across many micro-architectures and comes with a clean application programming interface allowing to easily build profiling tools on top of it.

Extending dataflow programs with throughput properties

In the context of multi-core processors and the trend toward many-core, dataflow programming can be used as a solution to the parallelization problem. By decoupling computation from communication, this paradigm naturally exposes parallelism in several ways. In this work we propose language extensions for expressing throughput properties over dataflow programs together with a run-time mechanism for the observation of events meaningful to compute the effective throughput. We show the limited impact of such mechanisms on the application overall performances. We also review existing run-time adaptation mechanisms that may be used in a dataflow context to satisfy throughput requirements.