Khaldoon Abugharbieh

25 nm chromium oxide lines by scanning tunneling lithography in air

An ambient scanning tunneling microscope is used to oxidize a thin Cr film to different oxidation states depending on the exposure conditions. These oxidation states have shown very different chemical and physical properties and can be used as positive or negative masks for lithography. Chromium oxide lines down to 25 nm have been formed.

Advancing high performance heterogeneous integration through die stacking

This paper describes the industrys first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. Optimization took place concurrently on multiple facets of the design which were necessary to successfully implement the 3-D integration. In particular, this paper outlines the choices that were made in terms of package substrate material and interposer resistivity in order to optimize 28Gb/s system channel characteristics. These choices were validated through extensive electrical simulation and test chip correlation. In addition, this paper describes the design and timing verification of inter-die interconnects, an area that the electronic design automation industry had not yet fully addressed. This paper further describes 3D thermal-mechanical modeling and analysis for package reliability. The modeling was performed to address package coplanarity issues and stresses imposed by the interposer on the active dice, the low-k dielectric material, the micro-bumps and the C4 attach. The results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities.

Interconnect and package design of a heterogeneous stacked-silicon FPGA

This paper reviews the interconnect and package design of a heterogeneous stacked-silicon FPGA. Up to five dice from two die types are mounted on a passive silicon interposer. A hardware- and software-scalable FPGA family can be created by mixing different combinations of these two die types. The FPGA, inside a low-temperature co-fired ceramic (LTCC) package, consists of two silicon die types - up to three FPGA ICs having a total of seventy-two 13.1-Gb/s transceivers (943.2 Gb/s full-duplex) and up to two GTZ ICs having up to sixteen 28.05-Gb/s transceivers (448.8 Gb/s full-duplex). Two types of interconnects are discussed: those joining the ICs through wires in the silicon interposer, and those connecting the 28-Gb/s transceivers through TSVs in the interposer to the package balls. An end-to-end 28.05-Gb/s channel simulation is discussed in the context of silicon interposer resistivity as well as package material and stack-up. In addition, this paper reviews 3D thermal-mechanical analysis confirming the reliability of heterogeneous stacked silicon.

A 10GHz wideband VCO with low KVCO variation

This paper presents a novel topology for a 10GHz voltage controlled oscillator (VCO). The design uses a differential delay cell architecture with four stages. It achieves a wide frequency range of (2-10) GHz and a maximum KVCO variation of 2.5 by using a voltage controlled resistor (VCR) that has a programmable size to reduce the impact of temperature and process corners variations. The design uses a 1V supply and consumes a maximum power of 18mW. It was extracted and simulated in 90nm CMOS technology.

A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

The paper presents the design of a 2.488 - 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. The transceiver makes use of a low-jitter LC PLL to enable high-reliability system design. A system modeling approach is also described, which is used for optimizing the architectural trade-offs. The design has 520fs RJrms and consumes 30.1 mW/Gbps at 11.2 Gbps.

An ultra low power 10 Gbps LVDS output driver

This paper describes a new topology and implementation of a 10 Gbps LVDS (low voltage differential signaling) voltage mode output driver designed for high speed data transfer applications. Using a positive feedback technique, the driver achieves ultra low power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is minimized and good signal integrity is achieved. The driver, which consists of a pre-driver and an output stage, consumes a total of 15.63mW at speed power. It provides a single ended output swing of 400mV and a common mode voltage of 1.25V which are compliant with LVDS standards. In measurements, the driver, which was a part of an equalizer chip, achieved peak to peak jitter of 11psec at 10Gbps. The chip is fabricated in a standard 2.5V/1.2V SiGe BiCMOS technology with 100 GHz peak ft, and packaged in a commercial LLP package.

A 10 Gbps loss of signal detector for high-speed AC-coupled serial transceivers in 28nm CMOS technology

This paper presents a 10 Gbps loss of signal (LOS) detector for high-speed AC-coupled serial transceivers. The detector is designed in 28nm CMOS and is capable of operating with a 29.5mV internal eye opening and a 67mV external eye opening at the input pads. It consumes 69uW from a 0.9V supply at 10 Gbps and properly asserts an LOS state in 6.8 nsec. A novel comparator topology, which is a part of the LOS circuit, is also presented. It compares a differential input to a differential reference voltage. Design and layout were implemented using Synopsys Custom Designer with 28nm CMOS device models. The LOS detector can reduce power consumption and bit error rate (BER) of serial transceivers.

Pull-up/pull-down line impedance matching methodology for high speed transmitters

A design and simulations methodology that detects and compensates for NMOS and PMOS transistor resistance variation is presented. The proposed methodology provides a robust mechanism to match the transmitter impedance to the line impedance which minimizes reflection and improves signal quality. A mixed signal approach, where an analog circuit detects the resistance variation, and a digital circuit uses the data to control the analog compensation circuit, is used. The system is designed in 28 nm CMOS process and simulated using Synopsys mixed mode simulation tools. Simulations show that worst case mismatch due to process, voltage and temperature variation is 2.7%.

Methodology for designing and verifying switched-capacitor sample and hold circuits used in data converters

This study presents a full methodological approach to designing and verifying differential sample and hold switched-capacitor circuits generally used in analogue-to-digital converters (ADCs). It provides a step-by-step process for translating system requirements such as signal-to-noise ratio and sampling frequency into ADC requirements and subsequently into operational amplifier topology and specifications. It also includes the design process of a switched-capacitor common mode feedback circuit to control the common mode output voltage. Furthermore, this study discusses the noise aspects of the switched-capacitor circuits. It also provides practical methods for verifying the stability of the system by using step voltage and step current techniques. A design and simulation example for a differential sample and hold switched-capacitor circuit operating in a system requiring a 5 MHz sampling frequency and a 6-bit ADC is provided. Mentor Graphics CAD tools were used in the design and the simulations process by using 180 nm complementary metal oxide semiconductors (CMOS) device models. This study can be used as a resource for the design engineers in the industry as well as the universities teaching graduate level advanced electronics and data converter courses.

A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver

This paper presents a new topology of a PMOS based LVDS voltage-mode output driver. This topology is designed to meet the requirements of low power consumption and high data rates applications. The driver, which consists of a pre-driver stage and an output stage, uses a positive feedback technique at the output stage to achieve line impedance matching and power saving. The pre-driver stage is used to set the drivers swing and common mode output voltage. The pre-driver and the output stage consume only 9mW of power at 3 Gbps speed while operating from a 1.8V voltage supply. The system is designed and simulated using CMOS 180nm technology and is fully compliant with LVDS output swing and common mode voltage specifications.