Khaled Grati

Design of Down-Sampling Processors for Radio Communications

This paper deals with design and implementation of digital filter processors to be used as down-samplers in wireless transceivers. We consider a homodyne direct conversion and propose an improved method to specify each stage of the cascade structure. The proposed scheme results in a globally compact implementation. The method is detailed for DECT standard and illustrated by a fixed point FPGA based implementation.

An Efficient Flexible Common Operator for FFT and Viterbi Algorithms

Todays telecommunication systems require more and more flexibility, and reconfiguration mechanisms are becoming major topics especially when it comes to multi-standard designs. This paper capitalizes on the Common Operator technique to present a new common operator for the FFT and Viterbi algorithms. In the present work, the FFT/Viterbi common butterfly is investigated where reuse and power consumption is traded against throughput. Performance comparisons with similar works are discussed in this paper.

Management architecture for green cognitive radio equipments

We assert in this paper that a management architecture has to be added to usual signal processing chain of radio equipment in order to integrate green management capabilities. The proposed architecture is based on our previous work on hierarchical and distributed cognitive radio (CR) architecture management for CR equipments. We assert that, at the level of an equipment, green radio can be considered as a subset of CR. A model-based approach is derived for the design of green radio equipments. As an example, we address in this paper a green scenario, which consists in bypassing the equaliser in function of signal to noise ratio and inter-symbol interference levels at a receiver. Then we show how we save energy, thanks to a complexity reduction. Both signal processing and implementations views are given for this scenario, which shows how our approach helps converting principles into reality. Copyright

Design and hardware implementation of digital channel selection processor for radio receiver

This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection filtering processor for radio receiver. For an homodyne wide-band RF receiver and sigma-delta modulator, two filtering cascade structures composed of 5 stages comb filter, FIR half-band filter and selector filter are compared. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators. Experimental results are given to evaluate performances and complexity of designed FPGA-based implementation.

Design and hardware implementation of digital channel selection decimating filter for multistandard receiver

This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection decimating filter for multistandard receiver. Authors propose an optimized multistage decimation filter for a front-end composed by an Homodyne wide-band RF receiver and sigma-delta modulator. Design flow of hardware architecture is presented through the choice of filter structure and architecture. Several results are given to evaluate performances and complexity of designed FPGA-based implementation that can support GSM, DECT and UMTS standard.

Design and implementation of cascade decimation filter for radio communications

This paper describes the design of a decimation filter for use with a 4/sup th/ order band-pass /spl Sigma//spl Delta/ modulator adapted for multi-standards wireless transceivers. The simulations undertaken demonstrated that GSM and DECT standards specifications are met by a filtering cascade structure composed of 5/sup th/ order comb filter, 2 half-band filter stages and a droop-correction filter. A fixed-point architectural design was defined and low-power FPGA implementation results are reported.

Statistical decision making method for cognitive radio

This work is about developing a decision making method, based on statistical modeling, for a cognitive radio receiver. By characterizing statistically the radio metrics, the intelligent equipment will be capable of making decisions on actions of reconfigurations, in order to adapt to the state of the environment. Through the adaptability of the radio receiver to the environment, we try also to reduce energy consumption by treating one scenario of reconfigurability which consists of switching off the equalizer when it is not necessary. Since this component is complex, the operation of turning it off should reduce the computational complexity of the receiver chain.

Cognitive engine design for cognitive radio

The work presented in this paper consists of designing a cognitive engine for a cognitive radio receiver. This engine must provide to the radio receiver the ability to be aware of its environment and to make decisions about actions of reconfiguration; these actions aim to adapt the receiver architecture to the state of the environment. In our design we develop a decision making method based on a statistical modeling of the environment. To show the decision performance of the method, we treat one example of a scenario of reconfiguration by applying the cognitive engine; it is to decide if there is a problem of a weak signal or not.

Power consumption models for decimation FIR filters in multistandard receivers

Decimation filters are widely used in communication-embedded systems. In fact, decimation filters are useful for implementing channel filtering or selection with low-computation complexity requirements. Many multistandard receiver designs that are required in ubiquitous embedded systems are based on a cascade of decimation filter processing. Filter number and implementation architectures have a significant impact on systemperformances, such as computation complexity, area, throughput, and power consumption. In this work, we present filter power consumption estimation models for FIR filters. Power consumption models were obtained froma large number of FIR filter syntheses using a direct form. Several curves that estimate power consumption were extracted from these synthesis results. Then, we have evaluated the impact of polyphase decomposition on power consumption of FIR filter and compared it with the direct form results. Some tips regarding power consumption were deduced for the polyphase implementation form. The aim of this work is to help a system designer to select an efficient implementation for FIR in terms of power consumption without having to implement and synthesize the different possible solutions. The proposed method is applied for STMicroelectronics libraries 90nm and 65 nm low power then validated with a use case of multistandard receiver designing.

Design and Implementation of a Reconfigurable Decimation and Channel Selection Filter for GSM and UMTS Radio Standards

This work presents a low-power multistandard decimation and channel selection filter architecture. The filter is suitable after an over-sampling sigma-delta converter and performs decimation in two stages. The first stage is a modified structure of the Cascade of Integrators-Combs (CIC) filter and allows reducing sampling rate downto only the double of the Nyquist frequency. The second stage composed of classical FIR filter, has relaxed specifications and performs channel selection. Implementation of the proposed filter for UMTS and GSM standards shows good filtering performances. The signal to ratio measured for UMTS is 14, 65 dB and for GSM 26,96 dB which satisfy largely the standards requirements. Implementation on ASIC 65-nm process technology shows power consumption gain of 14% in comparison to previously proposed low-power architecture.