Khaled M. Sharaf

An accurate analytical propagation delay model for high-speed CML bipolar circuits

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison to SPICE circuit simulation results show excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determined the optimum current i/sub 0/ (or load resistor R/sub L/) for a transistor of a certain emitter area when driven by a source of a voltage swing (/spl Delta/V) and slew time (t/sub r/). At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation delay time and improve the performance of high-speed CML circuits. >

Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits

An analytical model for calculating the propagation delay time of two-level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented. The analytical delay model accounts for all the device parasitics and the device sizes of the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level series-gated CML and ECL circuits for maximum speed (minimum delay). A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model.

High-Performance Digital VLSI Circuit Design

From the Publisher: High-Performance Digital VLSI Circuit Design is devoted to the analysis and design of digital VLSI CMOS, bipolar and BiCMOS circuits which are optimized for high-performance applications. The book starts by reviewing important background information in the area of MOS and bipolar device design and modeling. Detailed analysis and design of high-performance CMOS, CML/ECL, NTL and BiCMOS circuits is given. Achieving high-speed while maintaining low-power dissipation in digital circuits is addressed in depth in separate chapters. The book ends with a sample application area of high-performance design; namely the design of phase-locked loops. The book can be used as a reference for practicing IC designers and as a text for graduate and senior undergraduate students in the area of digital IC design.

Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications

A new active-pull-down nonthreshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an NMOS active-pull-down emitter-follower stage. A first-order analysis has been conducted to demonstrate the NMOS-APD concept. Simulation results based on 0.6 /spl mu/m BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4/spl times/ improvement in the load driving capability and 3.4/spl times/ improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV. >

BiCMOS active-pull-down non-threshold logic circuits for high-speed low-power applications

A new active-pull-down non-threshold logic (APD-NTL) BiCMOS circuit is presented and its performance has been evaluated and compared to that of standard NTL gate. The circuit utilizes an APD-NMOS emitter-follower stage. Simulation results based on 0.6-/spl mu/m BiCMOS technology indicate that at a power consumption of 1 mW/gate, the APD-NTL circuit offers 4/spl times/ improvement in the load driving capability and 3.4/spl times/ improvement in the speed compared to conventional NTL circuits for a load of 1 pF/gate and a logic swing of 800 mV. A comparison of critical-path delay has showed the superiority of the novel circuit over ECL circuits especially in the low-power region.<<ETX>>

Low-power differential CML and ECL BiCMOS circuit techniques

The performance of the different two-level series-gated CML BiCMOS schemes has been studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, have shown an improvement of 42% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating an the low power regime (<1 mW). Moreover, the BJT-MOS frequency divider configuration exhibits a high input sensitivity throughout the frequency range of operation. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit.<<ETX>>

High-Performance Bicmos Circuit Structures

This chapter presents high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier for static memory. Optimal use of the bipolar and MOS transistors pushes BiCMOS circuits to operate toward the limits of standard BiCMOS technologies. The chapter shows readers that the bipolar transistors in BiCMOS circuits not only serve as conventional output drivers, but also play an important role in circuit design such as for voltage clamps, current amplification, and current differential amplification. A generic 0.8µm complementary BiCMOS technology has been used in the circuit design. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuits, and the BiCMOS sense amplifier are improved by 20%, 250%, and 60% respectively. An analytical circuit delay model for DRV-CMOS/ECL interface circuits, which fits HSPICE simulation results, is addressed. The error between the model and the circuit simulator is within 4%. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V.

CMOS High-Performance Circuits

The dual purposes of this chapter are to review the design of recent high-performance CMOS circuits and to introduce and analyze novel all-N-logic single-phase high-speed pipelined dynamic CMOS circuits.

High-Performance CML, ECL and NTL Bicmos Circuits

In this chapter the performance of the different two-level series-gated CML BiCMOS schemes will be studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, show an improvement of 64% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating in the low power regime (< 1 mW). Moreover, the BJT-MOS frequency divider configuration a high input sensitivity throughout the frequency range of operation. In addition, a proposed BiCMOS latched-comparator shows favorable input voltage sensitivity over conventional bipolar design under low-power operation. Secondly, a brief overview of high-performance ECL circuit techniques is covered along with a rough comparison and evaluation of such techniques. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit.

High-Performance System Applications

High-performance integrated circuits, which can operate at frequencies in the GHz range, are required for applications such as wireless digital communications and fiber-optic data transmission. Parallel computers, high resolution graphics, and network backbones are among the many applications that could immediately benefit from inexpensive, compact, and easy-to-use giga-bit rate fiber-optic data links. Mobile communications have been also growing rapidly in this decade.