Richard X. Gu

Power dissipation analysis and optimization of deep submicron CMOS digital circuits

This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and /spl eta/, which reflects the drain induced barrier lowering, are also addressed.

All-N-logic high-speed true-single-phase dynamic CMOS logic

In this paper, a novel all-N-logic single-phase high speed dynamic CMOS logic is introduced and analyzed. The circuits achieve high speed by eliminating the need for the low-speed P-logic blocks. The use of all-N-logic allows the speed of the proposed circuits to be two to three times the speed of conventional CMOS dynamic circuits. An 2:1 frequency divider, using proposed ANL2 circuits, is simulated using 0.8 /spl mu/m CMOS technology with the operating clock frequency reaching as high as 1.5 GHz. A pipelined 8-b carry generator of five-stacked NMOS transistors, which operates at a clock rate of over 710 MHz, has also been simulated. Experimental results show that the proposed circuits operate over 910 MHz implemented in a 1.2 /spl mu/m CMOS technology.

An all-N-logic high-speed single-phase dynamic CMOS logic

In this paper, a new all-N-logic high speed pipelined single-phase dynamic CMOS logic is introduced and analysed. The use of an all-N-logic allows the speed of the proposed circuits to be 2-3 times the speed of conventional CMOS dynamic circuits. The operating speed of the proposed pipelined circuits is simulated using 0.8 /spl mu/m CMOS technology and reaches as high as 890 MHz. The pipelined 8-b carry generator of 5-stacked NMOSs which operates at a clock rate of over 550 MHz has been simulated.<<ETX>>

High-Performance Digital VLSI Circuit Design

From the Publisher: High-Performance Digital VLSI Circuit Design is devoted to the analysis and design of digital VLSI CMOS, bipolar and BiCMOS circuits which are optimized for high-performance applications. The book starts by reviewing important background information in the area of MOS and bipolar device design and modeling. Detailed analysis and design of high-performance CMOS, CML/ECL, NTL and BiCMOS circuits is given. Achieving high-speed while maintaining low-power dissipation in digital circuits is addressed in depth in separate chapters. The book ends with a sample application area of high-performance design; namely the design of phase-locked loops. The book can be used as a reference for practicing IC designers and as a text for graduate and senior undergraduate students in the area of digital IC design.

A new model for bipolar transistors at high current

A model for current gain and cutoff frequency falloff at high currents for bipolar transistors is proposed. The model is based on considering that the vertical and lateral base widening occur simultaneously for a typical bipolar transistor. The results of this model successfully fit Pisces-2B simulation results. >

Power dissipation in deep submicron CMOS digital circuits

In this paper, a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits is introduced. The model is based on Berkeley Short-Channel (BSIM) model and fits HSPICE simulation results well. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented.

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 /spl mu/m complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V. >

High-Performance Bicmos Circuit Structures

This chapter presents high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier for static memory. Optimal use of the bipolar and MOS transistors pushes BiCMOS circuits to operate toward the limits of standard BiCMOS technologies. The chapter shows readers that the bipolar transistors in BiCMOS circuits not only serve as conventional output drivers, but also play an important role in circuit design such as for voltage clamps, current amplification, and current differential amplification. A generic 0.8µm complementary BiCMOS technology has been used in the circuit design. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuits, and the BiCMOS sense amplifier are improved by 20%, 250%, and 60% respectively. An analytical circuit delay model for DRV-CMOS/ECL interface circuits, which fits HSPICE simulation results, is addressed. The error between the model and the circuit simulator is within 4%. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V.

High-Performance CML, ECL and NTL Bicmos Circuits

In this chapter the performance of the different two-level series-gated CML BiCMOS schemes will be studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, show an improvement of 64% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating in the low power regime (< 1 mW). Moreover, the BJT-MOS frequency divider configuration a high input sensitivity throughout the frequency range of operation. In addition, a proposed BiCMOS latched-comparator shows favorable input voltage sensitivity over conventional bipolar design under low-power operation. Secondly, a brief overview of high-performance ECL circuit techniques is covered along with a rough comparison and evaluation of such techniques. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit.

High-Performance System Applications

High-performance integrated circuits, which can operate at frequencies in the GHz range, are required for applications such as wireless digital communications and fiber-optic data transmission. Parallel computers, high resolution graphics, and network backbones are among the many applications that could immediately benefit from inexpensive, compact, and easy-to-use giga-bit rate fiber-optic data links. Mobile communications have been also growing rapidly in this decade.