Khee Yong Lim

A predictive semi-analytical threshold voltage model for deep-submicron MOSFET's

A compact threshold voltage model is developed for the prediction of deep-submicron MOSFETs scaling characteristic based on comprehensive 2-D device simulation, empirical formulation, and correlation to experimental data. The model incorporates the nonuniformities and nonlinearities from 2-D device physics, relates to process variables, and yet is efficient to use.

Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers

This paper for the first time successfully demonstrates a Logic-compatible, highly reliable, automotive-grade 16Mb flash macro with self- aligned, split-gate FG-based flash cell embedded into a 40nm Low Power CMOS with copper low-K interconnects. Key Features of the flash macro: Dual power supply with operation temperature from -40 to 150oC; Random Read access 10ns @ worst case condition; Low active and standby power; High raw endurance and data retention lifetime before using ECC. This technology provides large read current window which is compatible with both automotive MCU markets and low power mode tailored for smart card/industrial applications. The 16Mb Design test chip (DTC) with industry-leading cell size has demonstrated functionality with tight cell Vt and read current distributions. The SG NVM cell and erase gate are processed with self-alignment to gate spacer and polysilicon CMP (Chemical Mechanical Polishing) that can be easily integrated in a modular way to the standard logic process.

40nm Embedded Self-Aligned Split-Gate Flash Technology for High-Density Automotive Microcontrollers

This paper successfully demonstrates a logic- compatible, high performance and high reliability, automotive-grade 2.5V embedded NVM process extending over several generations. A high-density flash macro is used to debug process complexities which arise from the add-on modules. The modular approach is adopted for integrating self-aligned, floating-gate-based split-gate SuperFlash® ESF3 cell into 40nm CMOS logic process. Key features of the product-like Macro are dual power supply with input voltage fluctuations, wide operating temperature range from -40ºC to 150ºC, fast byte/word program under 10s and sector/chip erase under 10ms. The macro random read access time is only 8ns under worst case conditions. Key process monitors are characterization and yield of the Macro. Endurance was extended to 200k cycles and satisfy automotive grade requirement with wide read margin. Post-cycling data retention performs very well up to 150ºC. Wafer sort yield is in high double digits, with consistent wafer-to-wafer and within-wafer uniformity, showing good process control. The technology is suitable for high-speed automotive MCU, as well as IoT, smart card, and industrial MCU applications.

Functionality Demonstration of a High-Density 1.1V Self-Aligned Split-Gate NVM Cell Embedded into LP 40 nm CMOS for Automotive and Smart Card Applications

This paper successfully demonstrates a functional and reliable self-aligned, split-gate NVM cell, down to a very competitive and small cell size. This NVM cell is embedded into a 40 nm Low Power (LP) ground rule logic process with copper low-K interconnects. The self- alignment sequence with gate spacer and poly CMP (Chemical Mechanical Polishing) provides an optimized and small cell that can be easily integrated in the standard logic process, in a modular way. This is the first time that the industry has demonstrated a functional split-gate embedded Flash memory cell at 1.1V VDD. This embedded Flash process also yielded on a baseline 32 Mb high-density SRAM test chip as well as a 10% larger automotive-grade embedded Flash cell. We have further demonstrated reliability data that met the tightest market requirements, with a more relaxed 55 nm ground rule on a 16 Mb test array, using the same 40 nm LP process.