Khoi A. Phan

Enhanced dispositioning of reticle defects using the Virtual Stepper with automated defect severity scoring

As Optical Proximity Correction (OPC0 and Phase Shifting (PSM) become more and more commonly used for producing smaller features on wafer, the photomask (reticle) manufacturing, that is mask writing, inspection and repairing, and quality assurance become more challenging for both mask shops and wafer fabs. Consequently, a powerful defect analysis tool is needed to determine which defect is a nuisance defect, which defect needs to be repaired, and how good is the repair. It should have the capability for defect printability prediction and analysis of defect impact on device performance. In this paper, we will study and characterize the printability prediction of programmed defects on binary OPC masks by the Virtual Stepper System with its newly developed Automated Defect Severity Scoring (ADSS) function. AMDs defect test reticles HellOPC2 were used. The Virtual Stepper simulation and defect impact analysis results (the automatically calculated Defect Severity Score) will be compared to the SEM images and measurements of wafer prints using 193nm lithography. The results demonstrate that the Virtual Stepper System with its ADSS feature can provide its user with an automate, fast and accurate way of analyzing the impact of a defect. The Virtual Stepper System with ADSS function will be a suitable tool for photomask defect critically assessment in mask shops and wafer fabs.

Automatic defect severity scoring for 193-nm reticle defect inspection

Sub-wavelength lithography requires knowledgeable application of resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and phase shift mask (PSM). Use of RETs, in turn, requires that new photomask specifications and special requirements for mask defect printability be taken into consideration. This is especially true, as the photomasks critical dimensions become more aggressive (400 nm moving toward 300 nm). Traditionally, mask defect analysis and subsequent defect disposition has been accomplished by first performing automated reticle inspection, and then by visual inspection ultimately dependent on operator judgement. As the semiconductor industry moves to more challenging process generations this methodology is no longer viable for assessing the impact of a defect on the printed wafer. New techniques for more accurate, production-worthy defect printability analysis and defect disposition procedures are required. Developed at Numerical Technologies, Inc. is the Virtual StepperTM System that offers a fast, accurate software solution for defect printability analysis based on state-of- the-art lithography simulation techniques for advanced masks production using OPC and PSM. The newly developed Virtual Stepper System feature, Automatic Defect Severity Scoring (ADSS) provides fully automated and accurate defect impact analysis capability by calculating a consistent Defect Severity Score (DSS) for each defect detected by an inspection tool. DSS is an overall score that quantifies the impact of a given defect on surrounding features and can be used as a comprehensive indicator of defect printability. Taken into consideration, are not only printing defects, but defects which cause critical dimension (CD) errors altering a given process window.

Comparison of binary mask defect printability analysis using virtual stepper system and aerial image microscope system

As advanced process technologies in the wafer fabs push the patterning processes toward lower k1 factor for sub-wavelength resolution printing, reticles are required to use optical proximity correction (OPC) and phase-shifted mask (PSM) for resolution enhancement. For OPC/PSM mask technology, defect printability is one of the major concerns. Current reticle inspection tools available on the market sometimes are not capable of consistently differentiating between an OPC feature and a true random defect. Due to the process complexity and high cost associated with the making of OPC/PSM reticles, it is important for both mask shops and lithography engineers to understand the impact of different defect types and sizes to the printability. Aerial Image Measurement System (AIMS) has been used in the mask shops for a number of years for reticle applications such as aerial image simulation and transmission measurement of repaired defects. The Virtual Stepper System (VSS) provides an alternative method to do defect printability simulation and analysis using reticle images captured by an optical inspection or review system. In this paper, pre- programmed defects and repairs from a Defect Sensitivity Monitor (DSM) reticle with 200 nm minimum features (at 1x) will be studied for printability. The simulated resist lines by AIMS and VSS are both compared to SEM images of resist wafers qualitatively and quantitatively using CD verification.Process window comparison between unrepaired and repaired defects for both good and bad repair cases will be shown. The effect of mask repairs to resist pattern images for the binary mask case will be discussed. AIMS simulation was done at the International Sematech, Virtual stepper simulation at Zygo and resist wafers were processed at AMD-Submicron Development Center using a DUV lithographic process for 0.18 micrometer Logic process technology.

Metrology issues associated with submicron linewidths

The three conventional techniques--optical, low voltage scanning electron microscopy (LVSEM), and electrical linewidth measurement--continue to be employed, but each technique has unique applications, problems, and limitations. In this paper these techniques are investigated for submicron linewidth metrology. A great deal of emphasis is placed on the calibration of these tools and the potential for problems associated with the tools.

Reticle surface contaminants and their relationship to sub-pellicle defect formation

DUV lithography induced sub-pellicle particle formation continues to be a significant problem in semiconductor fabs. We have previously reported on the identification of various defects detected on reticles after extended use. This paper provides a comprehensive evaluation of various molecular contaminants found on the backside surface of a reticle used in high-volume production. Previously all or most of the photo-induced contaminants were detected under the pellicle. This particular contamination is a white “haze” detected by pre-exposure inspection using KLA-Tencor TeraStar STARlight with Un-patterned Reticle Surface Analysis, (URSA). Chemical analysis was done using Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS) and Raman spectroscopy.

Characterization of the manufacturability of ultrathin resist

A study was conducted to explore the manufacturability of ultrathin resist by focusing on two key issues, defects and etch resistance. Defects in ultrathin resist were characterized by optical inspection and scanning electron microscopy reviews. A number of representative defect types in the ultrathin resist/hardmask process were identified. With process optimization, defect density in ultrathin resist was reduced to levels that are comparable to that of a baseline 0.5 μm thick resist process on nontopographic wafers. Etch resistance sufficient for patterning metal–oxide–semiconductor transistor gate film stacks was demonstrated for a 100–150 nm thick resist layer.

Efficient and cost-effective photo defect monitoring

Manufacturing processes for submicron integrated circuits require strict process control for minimizing defects during the fabrication process. Defect densities are monitored on product wafers to determine whether the line maintains an acceptable yield level and to prevent any catastrophic downfall. However, defect detection is difficult for multilayer devices. A short loop defect monitor is often employed in the Photolithography area for inspection on an automated wafer inspection system like the KLA 213x. This monitor usually uses clean bare Silicon wafers which are processed through a Photocluster cell to define a resist pattern for defect inspection. In order to monitor a large set of equipment and resist types, a large quantity of clean Silicon wafers are required. The reuse of these silicon photo monitor wafers becomes difficult due to particles left on wafers after resist clean. Thus, the cost of daily photo defect monitor for equipment/process control becomes considerable. In this paper, we will discuss reusable thermal oxide test wafers as an alternative solution to Si wafers for a cost effective photo defect monitor. The required oxide thickness for I-line and DUV resists was calculated from Prolith/2 simulation. By using a special clean with Sulfuric Acid/Hydrogen Peroxide mixture (SPM) and followed by an Ammonium Hydroxide/Hydrogen Peroxide mixture (APM) for resist strip, very low particle counts were achieved for oxide substrate and better than those of Silicon wafers. Furthermore, due to low oxide thickness loss per clean cycle (1 - 2 A), oxide test wafers retain the optical characteristics for defect metrology tools to work without any recalibration. This makes the oxide photo defect monitor process very robust and production worthy. KLA defect data on unpatterned and patterned oxide test wafers for 20 or more reworks, will be shown. They will be compared to control Silicon test wafers. Some issues with exposure and focus condition and their effect on KLA defect detection will be discussed. Finally, a simple cost analysis model will show the potential saving benefit of oxide test wafer.

Photoresist process optimization for defects using a rigorous lithography simulator

Particulate contamination in photoresist is a major source of yield loss for CMOS processes. Yield loss due to such contamination is controllable by improved filtering. This paper explores the relation between particle size and line spacing for an i-line lithography process using a calibrated defect simulator.

ArF (193-nm) alternating aperture PSM quartz defect repair and printability for 100-nm node

Repair and printability of 193nm alternating aperture phase shift masks have been studied in detail in an effort to understand the overall production capability of these masks for wafer production at the 100nm node and below.

The application of submicron lithography defect simulation to IC yield improvement

Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosis of defect sources. This paper proposes a methodology for supplementing such experimental work with defect simulation. In particular, it is shown that lithography defect simulation can provide insight into defect mechanisms that cause major distortions in photoresist profiles. The nature of the distorted patterns can assist us in yield improvement efforts, since by comparing simulation results with the observed photoresist profiles on wafers, defect sources may be identified. Several lithography defect diagnosis examples are presented to demonstrate the approach.