David Ashby Steele

Photoresist process optimization for defects using a rigorous lithography simulator

Particulate contamination in photoresist is a major source of yield loss for CMOS processes. Yield loss due to such contamination is controllable by improved filtering. This paper explores the relation between particle size and line spacing for an i-line lithography process using a calibrated defect simulator.

The application of submicron lithography defect simulation to IC yield improvement

Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosis of defect sources. This paper proposes a methodology for supplementing such experimental work with defect simulation. In particular, it is shown that lithography defect simulation can provide insight into defect mechanisms that cause major distortions in photoresist profiles. The nature of the distorted patterns can assist us in yield improvement efforts, since by comparing simulation results with the observed photoresist profiles on wafers, defect sources may be identified. Several lithography defect diagnosis examples are presented to demonstrate the approach.

Methodology for the optimization of an i-line lithographic process for defect reduction

As device geometries shrink into the sub-half micron regime, controlling and reducing defect levels becomes increasingly important in both R&D and Manufacturing environments. Any delay in addressing the causes and cures of these yield killers can prolong the development cycle and production release of new product technologies. However, defect evaluation for a new lithography process on product wafers is difficult due to metrology limitation, substrate noises and previous layer defects. This problem is particularly pronounced for backend layers where differences in the metal grain sizes and reflectivity can confound defect inspection tools and can be picked up as false defects. Often yield learning is long delayed awaiting sort data, before lithographers can determine the beneficial effects of proposed manufacturing improvements. In this paper, we will discuss a methodology for optimizing an I-line lithographic process with the aid of a photo defect monitor. Clean Silicon wafers were fully processed through a photocluster cell to simulate the actual processing conditions for the product, then inspected on a KLA 2132 for pattern defects. An in-line low voltage SEM system was used to review and to classify defect types. In a case study presented here, post develop residue was found to be the predominant defect for a new I-line resist used in the backend layers of the 0.25 micrometer process technology. The resolution of the resist residue deposition problem was commenced by evaluating different processes with multiple puddles/rinses for their defect densities. Based on this work, a low defect developer process was chosen for further study. Other process variables such as resist profile, CD uniformity and Etch bias as well as electrical defect parameters were compared between the old and the new processes. The goal is to demonstrate that given equal performance in all other respects, a quick implementation of this new low defect process, prior to the sort yield confirmation, would not have any detrimental effect on device yield. An example of a non- killer defect, water stain droplets, discovered during the defect review will be shown. Further refining of the dry cycle in the process eliminated this cosmetic defect. Finally, the KLA defect trend chart will show an improvement in defect density with the new develop process.

Resist thickness optimization for multiple resists in a research and Development lithography environment

As production critical dimensions shrink from 0.25 micrometer generations down to 0.18 micrometer and farther, the demands of process control often have to be judged alongside throughput concerns. The resulting balance between these concerns is the result of a multitude of factors. In a lithography environment that produces multiple variants upon a similar device, one approach toward keeping resist processing uniformity down to manageable levels is to limit processing on a given track-stepper photocell to a single layer, with multiple variants upon only a few resist processes. If enough photo-cluster cells are present, this is a workable scheme. However, in the event that multiple devices are being produced out of a lithography environment with demanding resist capacity needs, inventive measures need to be taken in order to keep a manageable balance between throughput and process variation. More specifically, in the event that multiple resist processes are being managed within a single photo-cluster cell, resist process non-uniformity issues may arise due to the conflicting needs of the different resists. Therefore, due to the needs of multiple resist process support within a single photo-cell, any singular process may not be fully optimized. At AMDs Sub-micron Development Center (SDC) in Sunnyvale, California, a series of experiments were run with the intention of achieving the most optimized groups of I-line or DUV resist for a given resist thickness. Thickness output variables, such as range and thickness uniformity, were evaluated with respect to varying degrees of resist temperature within a single coater cup environment. From the initial results, further adjustments from the optimized resist temperature were performed in order to achieve a singular resist temperature for the entire resist block. In this paper, the limitations of track processing, specifically resist temperature control within a single resist coat cup environment, will be highlighted. Analyzed contour data generated by the Tencor/Prometrix FT750 will demonstrate the relationship between mean thickness, thickness uniformity and resist temperature changes, and how best to identify an optimized resist thickness for both single wafer and wafer to wafer processing. Lastly, from the output data collected, the best processing practice and placement of resists within a single coat cup environment can then be extended across an entire set of I-line and DUV photo-cells, leading to the optimization of several resists across a multiple track environment.

Photoresist defect diagnosis using a rigorous topography simulator

Defects in photoresist are often difficult to diagnose, because patterned wafer inspections can only be done after the photoresist is developed. In this paper, defect simulation is used to understand the relation between defects in the photoresist and the resulting photoresist profiles. It is shown that particles and bubbles in the photoresist translate into a wide variety of defective photoresist profiles. Knowledge of the relation between defects and photoresist profiles can assist in yield improvement efforts, since defects may be diagnosed by comparing simulated and observed photoresist profiles.

Novel approach for defect detection and reduction techniques for submicron lithography

Accurate and reproducible microlithography processing is critical for developing smaller and more dimensionally accurate semiconductor structures. As modern microprocessors and memory devices scale down to deep submicron dimensions, defects originating in the microlithography processes become increasingly effective in reducing yield. Careful and efficient methods of measuring the variability of these defect levels by utilizing a shortloop monitoring process is essential in controlling the quality of lithography process for these semiconductor devices. During the conventional photo process, a defect can result from either an external process variable (e.g. manual wafer handling), or an internal one from environmental sources (unclean equipment sets). Others may be related to the process parameters themselves; such as a pattern anomaly, marginal processing by the equipment, or a previous defect on the wafer creating a nucleation site for more defects. Since microlithography defects can arise from a variety of sources, adopting flexible and efficient methods of measuring their effects are essential in maximizing the yield. This study will discuss the methodologies used to characterize and monitor complete microlithography processing for two distinct cases: one in which the resist is mostly unexposed with the exception of a pattern of contact holes, and one in which most of the resist is exposed, leaving behind a developed pattern of resist lines. These two strategies, when used in conjunction and properly sampled in a defect metrology tool can lead to timely in-line feedback about the nature of possible processing defects present. Furthermore, the results of such a short loop may suggest continued short loop processing involving fewer processing steps to narrow the source.