Khoman Phang

Printed and Integrated CMOS Positive/Negative Refractive-Index Phase Shifters Using Tunable Active Inductors

This paper presents a printed and an integrated bi-directional tunable positive/negative refractive-index phase shifter utilizing CMOS tunable active inductors (TAIs). The printed phase shifter is comprised of a microstrip transmission line (TL), loaded with series varactors and a shunt monolithic microwave integrated circuit (MMIC) synthesizing the TAI. Using the TAI extends the phase tuning range and results in a low return loss across the entire tuning range. The integrated circuit (IC) phase shifter replaces the TLs with suitable lumped L-C sections. This enables integrating the entire phase shifter on a single MMIC, resulting in a compact implementation. The TAI used for both phase shifters is based on a modified gyrator-C architecture, employing a variable resistance to independently control the inductance and quality factor. The TAI is fabricated in the 0.13-mum CMOS process and operates from a 1.5-V supply. The TAI chip is used to implement the TL phase shifter, which achieves a phase of -40deg to +34deg at 2.5 GHz with less than -19-dB return loss from a single stage occupying 10.8 mm times 10.4 mm. The IC phase shifter is fabricated in the same process and achieves a phase from -35deg to +59deg at 2.6 GHz with less than -19-dB return loss from a single stage occupying 550 mum times 1300 mum.

Analysis of timing jitter in ring oscillators due to power supply noise

This paper presents a time-domain method for estimating the jitter in ring oscillators that is due to power supply noise. The method is used to analyze and compare the RMS cycle-to-cycle jitter of ring oscillators constructed from three possible delay elements: a CMOS digital inverter, a differential pair, and a current steering logic (CSL) inverter. Spice simulations verify the analysis method, and the results indicate that both the differential pair and CSL inverter provide superior supply noise immunity to the CMOS digital inverter.

A 0.13-

This letter presents a tunable positive/negative refractive index transmission line (TL) phase shifter utilizing active circuits. It comprises a microstrip TL loaded with series varactors and a shunt monolithic microwave integrated circuit (MMIC) to synthesize a tunable inductor. This implementation increases the phase tuning range and maintains the input and output matching of the phase shifter across the entire phase tuning range, while eliminating the need for bulky passive inductors. The phase shifter is capable of providing both positive and negative phase shifts. The MMIC tunable inductors are fabricated in a 0.13-mum CMOS process and operate from a 1.5-V supply. The phase shifter achieves a phase of -40deg to +34deg at 2.5GHz from a single stage with less than -19dB return loss, and better than 1.1-dB insertion loss at 2.5 GHz. The phase shifter has a 1-GHz bandwidth over which the return loss remains better than 12.1dB

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An optical receiver front-end consisting of a transimpedance amplifier and two post amplifiers consumes 1 mW from a 1 V supply and provides 210 k/spl Omega/ transimpedance gain at 75 Mb/s. A test chip in standard 0.35 /spl mu/m CMOS without low-threshold devices incorporates a charge pump for the biasing and tuning of MOS resistors.

m CMOS Phase Shifter Using Tunable Positive/Negative Refractive Index Transmission Lines

A transimpedance amplifier with differential DC-coupled photocurrent sensing was integrated in a standard 0.35 /spl mu/m CMOS process. It achieves 33 k/spl Omega/ transimpedance gain and a bandwidth of 255 MHz with a 2 pF photodiode capacitance. This design exhibits 40 dB power supply rejection ratio and an average input noise of (6.8pA)/(/spl radic/Hz). Power dissipation is 30 mW from a 3 V supply.

A 1 V 1 mW CMOS front-end with on-chip dynamic gate biasing for a 75 Mb/s optical receiver

This paper presents a balanced receiver structure suitable for wireless infrared data communications. The receiver provides a fixed photodiode bias voltage with the use of a regulated cascode input stage. Together with an active feedback loop used to eliminate dc photocurrents, the receiver implements ac coupling without the need for matching capacitors. Differential sensing of the photodiode current improves sensitivity. Designed for a 0.35 /spl mu/m digital CMOS process, simulation results show that the circuit consumes 12 mW at 3 V, provides 40 k/spl Omega/ transimpedance gain over a bandwidth of 200 MHz, and has a minimum power supply rejection ratio of 40 dB over the entire operating bandwidth.

A transimpedance amplifier with DC-coupled differential photodiode current sensing for wireless optical communications

This paper describes a CMOS optical preamplifier suitable for free-space, infrared wireless communications. The design is differential for improved power supply noise rejection, and an active cancellation scheme is used for eliminating dc photocurrents that are generated by ambient light. Making use of a 0.35-/spl mu/m CMOS process, the preamplifier provides a transimpedance gain of 20 k/spl Omega/ over a bandwidth from 1 MHz to 100 MHz and achieves 60 dB attenuation at dc.

Transimpedance amplifier with differential photodiode current sensing

In this paper, we present modifications to the constant-gm bias circuit and Miller-lead compensation of operational amplifiers which eliminate or minimize some of their shortcomings. First, we demonstrate how parasitic pad capacitance can cause instability in the constant-gm bias circuit, and show that the transconductance is constant only for specific bias conditions. Next, we suggest a new circuit topology that requires 75% less compensation capacitance to achieve stability. We also discuss problems with Miller-lead compensation that arise from temperature, process, and load variations. Finally, we present a new biasing technique to correct these problems, and, through simulation, demonstrate a 40∘ improvement in phase margin over load current variations.

A 3-V CMOS optical preamplifier with DC photocurrent rejection

This paper presents a low voltage programmable continuous-time filter for hearing aids. The filter uses an analog circuit technique employing on-chip charge pumps called dynamic gate biasing (DGB). A simple method for reducing the ripple from the DGB charge pumps is presented. The principle of DGB is experimentally verified through the implementation of a programmable g/sub m/-C biquadratic filter. Designed in 0.35 /spl mu/m CMOS, the filter operates from 1.2 V and dissipates 16 /spl mu/W, provides 62.3 dB dynamic range at -45 dB THD and can realize lowpass, bandpass and highpass filter responses.

Improvements in biasing and compensation of CMOS opamps

This paper presents a novel differential 0.13mum CMOS active inductor circuit, which is employed in the design of an integrated negative refractive index metamaterial phase shifter. The active inductor circuit employs a digital/analog tunable feedback resistance to allow controlling both the inductance and the quality factor. The inductance is tunable from 2.5nH to 13.6nH at 5GHz while having a fixed peak quality factor of 100. This results in a phase shift of 36.7deg/stage, at 5GHz, with less than 0.67dB insertion loss