Ki-Ho Baik

TaN-based EUV mask absorber etch study

Extreme ultraviolet lithography (EUVL) is one of the leading candidates for the next generation lithography. As the requirement on critical dimension (CD) and side wall profile control becomes ever stringent as minimum feature sizes keep shrinking following the Semiconductor Industry Association (SIA) roadmap, the patterning of the EUV mask absorber material, cost of ownership (COO) of mask, and the capability for defect free EUV masks become the crucial path in enabling the overall success of EUV lithography. The purpose of this study is to understand the etch characteristics in TaN-based EUV mask absorber etch, which will enable us to determine robust process condition in terms of CD performance and profile control. In this paper, CD bias performance in TaN-based EUV mask absorber etching is investigated within inductively coupled plasma (ICP) of fluorine-containing and chlorine-containing gas chemistries. The effects of etch parameters, such as plasma source power, bias power, and pressure, on the CD bias are evaluated through design of experiments (DOE). Some other etching characteristics like etch rate and selectivity are also correlated to the CD performance and etch profile to understand the basic etch mechanism in TaN etch. Latest etch results of the TaN-based absorber are also presented.

100-nm OPC mask patterning using raster-scan 50-kV pattern generation technology

ABSTRACT The complexity of photomasks is rapidly increasing as semiconductor devices are scaled down and optical proximitycorrection (OPC) becomes commonplace. Raster scan architectures are well suited to the challenge of maintaining maskthroughput despite these trends. Electron-beam techniques have the resolution to support OPC requirements into theforeseeable future. The MEBES ® eXara mask pattern generator combines the resolution of a finely focused electronprobe with the productivity and accuracy of Raster Graybeam patterning. Features below 100nm can be created, andOPC designs are produced with consistent fidelity. Write time is independent of resist sensitivity, allowing high-doseprocesses to be extended, and relaxing sensitivity constraints on advanced chemically amplified resists. The system isdesigned for the production of 100nm photomasks, and w ill support the development of 70nm masks.Keywords: MEBES, electron beam, lithography, photomask, graybeam, CAR, OPC 1. INTRODUCTION

PAB and PEB temperature gradient methodology for CAR optimization

Chemically amplified resist (CAR) performance can be greatly influenced by post apply bake (PAB) and post exposure bake (PEB) conditions. The difficulty with optimizing these conditions for photomask process is cost and time. In typical wafer CAR resist development, multiple wafer splits and skews can be rapidly processed with relatively low cost and fast turn around time, whereas in photomask processing each ebeam-written mask with a set of DOE conditions can be expensive and time consuming to produce. This paper discusses a novel mask design and testing methodology that allow for many combinations of PEB and PAB conditions to be evaluated with one mask. In brief, this methodology employs orthogonal PAB and PEB thermal gradients across a plate. Some thermal profile, darkloss, resist top down critical dimensions (CD), and SEM cross section image results will be shared and discussed.

REAP (raster e-beam advanced process) using 50-kV raster e-beam system for sub-100-nm node mask technology

A chemically amplified resist (CAR) process has been recognized as an approach to meet the demanding critical dimension (CD) specifications of 100nm node technology and beyond. Recently, significant effort has been devoted to optimizing CAR materials, which offer the characteristics required for next generation photomask fabrication. In this paper, a process established with a positive-tone CAR from TOK and 50kV MEBES eXara system is discussed. This resist is developed for raster scan 50 kV e-beam systems. It has high contrast, good coating characteristics, good dry etch selectivity, and high environmental stability. The coating process is conducted in an environment with amine concentration less than 2 ppb. A nitrogen environment is provided during plate transfer steps. Resolution using a 60nm writing grid is 90nm line and space patterns. CD linearity is maintained down to 240nm for isolated lines or spaces by applying embedded proximity effect correction (emPEC). Optimizations of post-apply bake (PAB) and post-expose bake (PEB) time, temperature, and uniformity are completed to improve adhesion, coating uniformity, and resolution. A puddle develop process is optimized to improve line edge roughness, edge slope, and resolution. Dry etch process is optimized on a TetraT system to transfer the resist image into the chrome layer with minimum etch bias.

Raster scan patterning solution for 100- and 70-nm OPC masks

Photomask complexity threatens to outpace mask pattern generator productivity, as semiconductor devices are scaled down and optical proximity correction (OPC) becomes commonplace. Raster scan architectures are well suited to the challenge of maintaining mask throughput and mask quality despite these trends. The MEBES eXara mask pattern generator combines the resolution of a finely focused 50 keV electron beam with the productivity and accuracy of Raster Graybeam writing. Features below 100 nm can be imaged, and OPC designs are produced with consistent fidelity. Write time is independent of resist sensitivity, allowing high-dose processes to be extended, and relaxing sensitivity constraints on chemically amplified resists. Data handling capability is enhanced by a new hierarchical front end and hiearchical data format, building on an underlying writing strategy that is efficient for OPC patterns. A large operating range enables the MEBES eXara system to support the production of 100 nm photomasks, and the development of 70 nm masks.

High-productivity mask writer with broad operating range

Photomask complexity increases rapidly as semiconductor devices continue to shrink and as optical proximity correction becomes commonplace. This trend stresses the performance of mask pattern generators due to the increase in both primary and subresolution features. However, the next-generation MEBES raster scan architecture is well-suited to the challenge of maintaining throughput regardless of increases in pattern complexity. In addition, this new system provides an operating envelope that is sufficiently broad to expose all practical resist materials with a fixed number of writing passes. Write time is independent of material sensitivity, which has the benefits of allowing high-dose processes to be optimized, and also of supporting a wide selection of chemically amplified resist candidates for critical mask patterning. The new system shows the promise of being extendible to the 70 nm technology generation.

The design and qualification of the TEL CLEAN TRACK ACT M photomask coating tool at Intel

As photomask complexity has increased, mask manufacturing has become significantly more challenging. Tightening specs on defect performance, resolution, and CD control have pushed mask manufacturing to achieve levels that nearly match wafer capabilities. To meet wafer manufacturing needs, mask production requires high yield and quick turn-around time, resulting in an increased demand for very high equipment reliability. In-line resist coating capability is important to meet these demands; both for robust 2nd level phase-shift coating processes, and the enablement of advanced 1st-level process development with new resists and new resist process conditions. Intel Corporation worked with Tokyo Electron Ltd (TEL) to bring one of the first CLEAN TRACK ACT M (ACT M) units through design, acceptance tests and into manufacturing. TELs CLEAN TRACK ACT M is a resist coating tool based on the CLEAN TRACK ACT12 (ACT 12) wafer manufacturing platform, and contains multiple mask-specific modules including advanced softbake oven units, edge-bead removal modules, and cleaning systems. After setup and optimization, the tool shows impressive performance, (for example, within-plate thickness uniformity of < 8A (3s) for certain processes). The motivation of the tool layout is discussed thoroughly. Elements of the module designs and their performance are shown. The acceptance testing performance is presented and includes: cleaning capabilities, oven performance, thickness performance, coating defect levels and edge bead removal capabilities. Finally, there is a limited discussion of manufacturing performance.

Real time monitoring of reticle etch process tool to investigate and predict critical dimension performance

As mask pattern feature sizes shrink the need for tighter control of factors affecting critical dimensions (CD) increases at all steps in the mask manufacturing process. To support this requirement Intel Mask Operation is expanding its process and equipment monitoring capability. We intend to better understand the factors affecting the process and enhance our ability to predict reticle health and critical dimension performance. This paper describes a methodology by which one can predict the contribution of the dry etch process equipment to overall CD performance. We describe the architecture used to collect critical process related information from various sources both internal and external to the process equipment and environment. In addition we discuss the method used to assess the significance of each parameter and to construct the statistical model used to generate the predictions. We further discuss the methodology used to turn this model into a functioning real time prediction of critical dimension performance. Further, these predictions will be used to modify the manufacturing decision support system to provide early detection for process excursion.

Study of rigorous effects and polarization on phase shifting masks through simulations and in-die phase measurements

As lithography mask process moves toward 45nm and 32nm node, phase control is becoming more important than ever. Both attenuated and alternating PSMs (Phase Shift Masks) need precise control of phase as a function of both pitch and target sizes. However conventional interferometer-based phase shift measurements are limited to large CD targets and requires custom designed target in order to function properly, which limits phase measurement. Imaging simulations, both, in a rigorous and a Kirchhoff regime, show the dependency of the phase in the image plane of a microlithography exposure tool on numerical aperture, polarization, and on the so-called balancing of the mask for features close to the size of the used wavelength. For these feature sizes, the image phase does not coincide with the etch depth equivalent phase calculated from the nominal depth and optical constants of the shifter material. Additionally, for PSMs generating phase jumps deviating from 180°, the resulting phase in the image plane of a microlithography exposure tool depends on the transmitted diffraction orders through the aperture of the imaging system. Consequently Zeiss, in collaboration with Intel, has started the development of a laterally resolving Phase Metrology Tool (Phame) for in-die phase measurements. In this paper we present this optical metrology tool capable of phase measurement on individual line/spaces down to 120nm half pitch. Alternating PSM, Attenuated PSM, Cr-less masks were measured on various target sizes and simulations were performed to further demonstrate the capability and implication of this new method to measure the scanner relevant phase in-die, taking into account NA, polarization, and rigorous effects.

CD bias control with in-situ plasma treatment in EPSM photomask etch

As mask feature size decreases, etch bias control during Cr and shifter etch becomes more critical factor in Embedded Phase Shifter Mask (EPSM) mask making processes. Since the etching characteristics of the shifter materials, Molybdenum Silicide (MoSi), are sensitive to etching surface condition, Critical Dimension (CD) performance of the shifter layer strongly depends on incoming surface condition from Cr etch. In this paper, lateral etch component of MoSi etch was investigated as a function of various substrate conditions so that a new in-situ plasma treatment was suggested to control the CD bias during MoSi etch. The CD performance was characterized within the surface treatment plasmas and also correlated with some plasma parameters and substrate temperature. As a result, it was found that plasma surface modification could be an in-situ technique to better control the shifter CD in EPSM process and an essential option for redundancy tools in mask production environment.