Ki-Jae Song

Low Power Noise Multilayer PCB with Discrete Decoupling Capacitors Inside

In this paper, we describe the design and implementation of the low noise interconnection (low power plane impedance) in multilayer boards using embedded discrete capacitor technology. To obtain the low noise solutions over a wide range of operating frequency, the overshoot resonances excited at some frequencies should be firstly analyzed. Some resonances make the signal and power integrity problems in the high speed digital boards. To solve these issues related with overshoot resonances, the equivalent circuit model for a PDN should be developed. It is well known that the transmission line matrix (TLM) model serves a proper design method for power delivery network (PDN) including the power/ground plane, via, capacitors, and so on. As using this TLM method, the power impedance and overshoot resonance for the designed PDN can be estimated. Therefore, the power impedance and some resonances on PDN can be easily approached and optimized for low noise interconnection design. The discrete capacitors are conventionally used to minimize the power impedance at any frequency band where the impedance of the decoupling capacitor is lower than that of the power/ground planes pair. However, the increase of equivalent series inductance (ESL) in the discrete capacitor degrades the low noise frequency bandwidth under the multilayer board environments. It is noted that the embedded discrete capacitor structure presented in this paper can be used to maintain the parasitic inductance of the decoupling capacitor as low as possible to decrease the overshoot of the resonance frequency. According to our experimental results, the resonance magnitude and power noise characteristic are from 15 ? to 1 ? and from -53 dBm to -64 dBm, respectively.

A Serial Optical Link Based Memory Test System for High-Speed and Multi-Parallel Test

A novel memory optical test solution is proposed and experimentally evaluated for at-speed DDR2-SDRAM test using a commercial automatic test equipment (ATE). Combination of an optical signal splitting scheme and SerDes (Serializer/De-Serializer) technique based on FPGA (Field programmable gate array) allows the high-speed multi-parallel memory test with reduced channel resources. Owing to the SerDes, optical fiber channels are reduced by more than 87 percent and the number of optical modules including transmitter/receiver dramatically decrease to 95 percent, compared with a conventional optical test interface system. Furthermore, the proposed system can optically expand the tester resource by 4 times using a 1 × 4 optical splitting scheme. We evaluated the signal integrity of 28 layer PCB operating at 3.125 Gbps with three-dimension electromagnetic simulation to obtain more reliable system for memory testing. Consequently, for the first time to the best of our knowledge, we realized an optical SerDes interconnect system for a memory test tester and demonstrated an actual write/read function test of DDR2-SDRAM.

Low‐power noise multilayer PCB with discrete decoupling capacitors inside

In this paper, we describe the design and implementation of the low noise interconnection (low power plane impedance) in multilayer boards using embedded discrete capacitor technology. To obtain the low noise solutions over a wide range of operating frequency, the overshoot resonances excited at some frequencies should be firstly analyzed. Some resonances make the signal and power integrity problems in the high speed digital boards. To solve these issues related with overshoot resonances, the equivalent circuit model for a PDN should be developed. It is well known that the transmission line matrix (TLM) model serves a proper design method for power delivery network (PDN) including the power/ground plane, via, capacitors, and so on. As using this TLM method, the power impedance and overshoot resonance for the designed PDN can be estimated. Therefore, the power impedance and some resonances on PDN can be easily approached and optimized for low noise interconnection design. The discrete capacitors are conventionally used to minimize the power impedance at any frequency band where the impedance of the decoupling capacitor is lower than that of the power/ground planes pair. However, the increase of equivalent series inductance (ESL) in the discrete capacitor degrades the low noise frequency bandwidth under the multilayer board environments. It is noted that the embedded discrete capacitor structure presented in this paper can be used to maintain the parasitic inductance of the decoupling capacitor as low as possible to decrease the overshoot of the resonance frequency. According to our experimental results, the resonance magnitude and power noise characteristic are from 15 ¿ to 1 ¿ and from -53 dBm to -64 dBm, respectively.

Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages

This paper introduces the package test interface fixture with low cost test topology, high electrical performances, and compatibility with fine pitch packages. The proposed fixture demonstrates electrical performance using special jig and mobile DDR2.

Frequency Synthesizer Using Dual Offset Mixing for Low Phase Noise and Narrow Resolution

This paper introduces a low in-band phase noise synthesizer with narrow frequency resolution. In order to improve the noise characteristic, the output frequency of the voltage controlled oscillator is converted into a fixed low IF signal by two mixers. Therefore, the N division ratio is relatively reduced, which means the minimization of the in-band phase noise. To confirm the noise performances, this synthesizer is simulated and analyzed through the phase domain noise model. This paper presents the simulation results for the phase noise, spurious, and acquisition time

Analysis of coupled simultaneous switching noise induced from power delivery network in adjacent switching circuit

This paper investigates the estimation of the coupled Simultaneous Switching Noise (SSN) induced from Power Delivery Networks (PDNs) in memory test boards. When the signal changes its reference plane in the board, voltage fluctuation occurs that induces the SSN in the PDN. This induced SSN affects other signals in the test board, reducing signal quality and test reliability. To avoid this problem, precise analysis and modeling become necessary. To demonstrate the analysis model, we designed and fabricated a 6-layer Printed Circuit Board (PCB) on which 11 clock buffers (noise sources) and signal traces (victim lines) were installed. The scattering parameters were measured from 10MHz to 3GHz, and the signals in the victim lines were also measured using 20GHz bandwidth oscilloscope. The PDN impedances and transfer characteristics with/without decoupling capacitors were simulated using both full-wave and circuit simulations, which coincide quite well with the measured data. Finally, we confirm the validity of the proposed simulation model, and we propose a design methodology to minimize the coupled SSN by installing decoupling capacitors on the test board.

Designing a high speed system with amplitude and phase noise reduction effects

In this paper, we introduce a method for reducing the amplitude and the phase noise to achieve low noise and high speed system. Obtaining a good signal and maintaining the power integrity, by eliminating noise development and propagation are constant requirements. However, the increase of the interconnection complexity in the multilayer PCBs (Printed Circuit Boards) usually creates a questionable noise source that can be caused by either the signal mismatch or the power disturbance. Especially, the SSN (Simultaneous Switching Noise) and coupled noise need to be deliberately examined for reducing the overall noises. After the noise generation and propagation are analyzed, the amplitude and phase noise on the high speed signal will be investigated by using the integrated simulation circuit model (ISCM) technique and according to some related experiments. In this paper, we also propose a multi-PDN structure (M-PS) for minimizing the noise generation and propagation within the wanted frequency band. This method uses an additional core PDN to control the values of the R, L, and C parameters on the equivalent circuit of the systems PDN.

Miniaturized electromagnetic band-gap structure to suppress simultaneous switching noise

In this paper, we present a method to miniaturize electromagnetic band-gap (EBG) structure. EBG is used to suppress noise occurred as tons of switching devices switch on and off simultaneously. In the proposed model, slits exist on both power and ground planes of power distribution network (PDN), which is called 3-D EBG due to the geometric configuration. The method to miniaturize EBG structure is based on signal return path theorem. Two-layered 3-D EBG structure is fabricated, and 3-D full-wave simulator, HFSS, is used to calculate S21 parameter. The measured and calculated S21 parameter shows high isolation, suppressing the noise under -40 dB at the frequency range of 2.8 GHz to 8.3 GHz. Finally the performance of the proposed 3-D EBG structure is compared with the other two 2-D EBG structures and shows its superiority to them.

SSN noise analysis caused by adjacent driving circuits

In this paper, we propose an SSN (Simultaneous Switching Noise) analysis method, which is caused by adjacent driving circuits. The driving circuits consist of 11 clock buffers. Each circuit has its own transmitting and receiving part, and the transmission line was designed to experience several reference changes to get to the load. The effect occurred from reference change of signals on the characteristic of signal integrity was observed in the victim region. A CDCVF2310 clock buffer that operates up to 200 MHz at the supply voltage of 3.3V, five FIN 1027 drivers, and five FIN 1028 receivers were used as a noise source. The clock buffers create SSN by switching simultaneously, which affects the power supply voltage quite a lot. With the clock buffers operating at the frequency 200 MHz, we measured voltage fluctuations in the supply DC voltage of 3.3 V. We also used decoupling capacitors to control the impedance of PCBs. Transmission line matrix (TLM) method was used to model and simulate the power distribution network of PCB. Adding decoupling capacitors with variations in the number and the distance from the power pins of a chip, the impedance of PCB was measured using a vector network analyzer in the frequency range from 10 MHz to 3 GHz. From the measured results, we made an impedance profile for PCB that gives a design guide for how many and where to place decoupling capacitors. Finally the level of signal distortion is compared and the differences between them are discussed.