Hun-kyo Seo

Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages

This paper introduces the package test interface fixture with low cost test topology, high electrical performances, and compatibility with fine pitch packages. The proposed fixture demonstrates electrical performance using special jig and mobile DDR2.

SSN noise analysis caused by adjacent driving circuits

In this paper, we propose an SSN (Simultaneous Switching Noise) analysis method, which is caused by adjacent driving circuits. The driving circuits consist of 11 clock buffers. Each circuit has its own transmitting and receiving part, and the transmission line was designed to experience several reference changes to get to the load. The effect occurred from reference change of signals on the characteristic of signal integrity was observed in the victim region. A CDCVF2310 clock buffer that operates up to 200 MHz at the supply voltage of 3.3V, five FIN 1027 drivers, and five FIN 1028 receivers were used as a noise source. The clock buffers create SSN by switching simultaneously, which affects the power supply voltage quite a lot. With the clock buffers operating at the frequency 200 MHz, we measured voltage fluctuations in the supply DC voltage of 3.3 V. We also used decoupling capacitors to control the impedance of PCBs. Transmission line matrix (TLM) method was used to model and simulate the power distribution network of PCB. Adding decoupling capacitors with variations in the number and the distance from the power pins of a chip, the impedance of PCB was measured using a vector network analyzer in the frequency range from 10 MHz to 3 GHz. From the measured results, we made an impedance profile for PCB that gives a design guide for how many and where to place decoupling capacitors. Finally the level of signal distortion is compared and the differences between them are discussed.