Ki-seok Kwon

Design space exploration and implementation of a high performance and low area Coarse Grained Reconfigurable Processor

Coarse Grained Reconfigurable Architectures (CGRAs) have played a key role in the area of domain specific processors due to their programmability and runtime reconfigurability. The Coarse Grained Array (CGA) structure enables target designs to achieve high performance, but it is easy to fall into over-design in term of area. Moreover, the network overhead between the function units (FUs) seriously degrades its clock speed. In this paper, we propose a high performance CGRA that facilitates design space exploration (DSE) to reduce these overheads. It employs a concept of building blocks, named mini cores, to mitigate overhead involved in DSE that aims to achieve high clock speed and small area in the target design. The proposed approach reduces the design time more than 100 times compared with previous design. Experimental results show that the implemented architecture reduces logic area by 14.38% and improves clock frequency by 59.34% without performance loss.

Pipelined Cartesian-to-Polar Coordinate Conversion Based on SRT Division

This brief proposes a new Cartesian-to-polar coordinate conversion technique based on the radix-4 SRT division. The coarse quotient is used to derive the magnitude and the coarse phase by referring to tables, while the fine quotient is applied to linearly interpolate the fine phase to be added to the coarse phase. Compared to the CORDIC-based techniques, the proposed conversion requires less internal word-length and provides parallelism between internal stages, resulting in reduced computation latency and small chip area. A prototype chip designed using 0.25-mum CMOS technology occupies 0.203 mm2, and post-layout simulations show maximum frequency of 400 MHz and power consumption of 170 mW at 2.5 V.

Design of high-performance 32-bit embedded processor

This paper describes the implementation of high-performance 32-bit embedded processor, Core-A. Core-A processor has unique instruction set architecture(ISA) in the form of reduced instruction set computer (RISC). Especially, Core-A processor has several unique features for code density and DSP applications. Since Core-A processor is described using Verilog HDL, it can be customized for a given application and synthesized for an ASIC or FPGA target. Also, software tool chain including compiler, assembler, linker, and debugger has been developed for Core-A processor. Core-A processor with separate cache is implemented using a 0.18 mum 1P4M CMOS process and the real-time edge detection system is designed with Altera FPGA for evaluation system.

Ultra-low-power voice trigger for wearable devices

We introduce an ultra-low-power digital signal processor (DSP) solution for wearable applications with high performance. It employs three-issue VLIW architecture with the major low-power techniques and implemented with 95K gates in Samsung 28LPP process and runs up to 200MHz. The experimental results demonstrate that a voice trigger application can operate at 6.1MHz under 0.15mW power consumption.

The effect of CF4 and CHF3 gas on the etching characteristics of Er-doped glass

In this study, AFD (aerosol flame deposition) was used to prepare Er-Doped high-purity silica glass for applications to the planar amplifying waveguide. The effects of etching gas on the etching characteristics of the glass film were examined based on the etching rate and the surface roughness of the waveguide. The glass composition in the experiment can be represented as 62SiO 2 -30B 2 O 3 -8P 2 O 5 + x wt% Er 2 O 3 (x=0, 0.2, 0.5).