Ki Yeol Byun

Characterization of germanium/silicon p-n junction fabricated by low temperature direct wafer bonding and layer exfoliation

The current transport across a p-Ge/n-Si diode structure obtained by direct wafer bonding and layer exfoliation is analysed. A low temperature anneal at 400 °C for 30 min was used to improve the forward characteristics of the diode with the on/off ratio at −1 V being >8000. Post anneal, the transport mechanism has a strong tunnelling component. This fabrication technique using a low thermal budget (T ≤ 400 °C) is an attractive option for heterogeneous integration.

Comprehensive investigation of Ge–Si bonded interfaces using oxygen radical activation

In this work, we investigate the directly bonded germanium-silicon interfaces to facilitate the development of high quality germanium silicon hetero integration at the wafer scale. X-ray photoelectron spectroscopy data is presented which provides the chemical composition of the germanium surfaces as a function of the hydrophilic bonding reaction at the interface. The bonding process induced long range deformation is detected by synchrotron x-ray topography. The hetero-interface is characterized by measuring forward and reverse current, and by high resolution transmission electron microscopy.

Low-Temperature Fabrication of Germanium-on-Insulator Using Remote Plasma Activation Bonding and Hydrogen Exfoliation

Low-temperature germanium to silicon wafer bonding was demonstrated by in situ radical activation and bonding in vacuum. After low temperature direct bonding of Ge to Si followed by annealing at 200 and 300°C, advanced imaging techniques were used to characterize the bonded interface. The feasibility of transferring hydrogen-implanted germanium to silicon with a reduced thermal budget is also demonstrated. Germanium samples were implanted with hydrogen and a two-step anneal was performed. The first anneal performed at low temperature (≤150°C for 22 h) to enhance the nucleation of hydrogen platelets. The second anneal is performed at 300°C for 5 min and is shown to complete the exfoliation process by triggering the formation of extended platelets.

Hot carrier (HC) and bias-temperature-instability (BTI) degradation of MuGFETs on silicon oxide and silicon nitride buried layers

The results are reported of an experimental study of the hot carrier (HC) and bias-temperature-instability (BTI) reliability of MuGFETS, fabricated on SOI wafers with silicon oxide and silicon nitride buried layers. N- and P-channel devices of 65 nm long and 42nm or 32nm wide channels were stressed and measured at room temperature and at 125°C. A complicated picture emerges: HC degradation is dominant in n-MuGFETs whereas both HC and BTI mechanisms are active concurrently in p-MuGFETs under hot carrier stress. When HC degradation dominates, the wider fin devices tend to degrade more than the narrower; the reverse is generally true for BTI degradation.

Creating Thin-Film Silicon on Flexible Substrates using Adhesive Bonding and Wet Etching

A method to create thin-film silicon from SOI wafers on a flexible substrate, PEN (polyethylene naphthalate) was developed. Indirect bonding was utilized to bond silicon wafers to PEN, and chemical mechanical polishing (CMP) and wet etching were performed to remove the silicon substrate. An adhesive polymer, BCB (benzocyclclobutene), was spin-coated on the wafers followed by a heated pre-curing step to bake out the volatile solvents prior to bonding to ensure a void-free bond. Post-bonding annealing was performed to increase the bond strength; the combination of 150C for 48-hours was found to be an optimum anneal process. After bonding the silicon substrates were ground by CMP leaving approximately 100 μm for removal by conventional wet etching. The etchant used was a mixture of hydrofluoric acid (HF), nitric acid (HNO3), and glacial acetic acid (CH3COOH ) in a ratio of 6: 3: 1. This ratio resulted in a high etch rate of 4 to 5 μm/min. The silicon dioxide the in SOI wafers acts as an etch stop layer due to the high selectivity of the etchant for silicon compared to SiO2 [1]. Since the thermal expansion properties are different for silicon, BCB and PEN, residual stress is expected in the final bonded structure [2]. The stress calculated using the coefficients of thermal expansion of the materials was 21.8 MPa, which corresponds to 0.017 % compressive strain. After CMP the thinned bonded samples displayed extensive bending (Figure 1). The radius of curvature measured on the thinned bonded sample was 208 mm. The thinned silicon wafer has decreased stiffness which allows more bending of the bonded material. The stress experienced by the silicon is increased significantly because of the increase in strain caused by the bending of the ground sample. The stress in the samples was measured using Raman spectroscopy at different points in the thinning process. A future development of double transferring to bond PEN on the opposite side of thin film was proposed. Residual tensile strain can be created in the silicon using this method causing increased hole or electron mobility [3].

Pattern Stamping Using Exfoliation for Heterogeneous Integration

The heterostructure composed of alternating layers is a promising both for high performance nano-electronic devices, and as a potential path for integrating optoelectronic devices. Recent advances in terms of performance and scalability of Germanium channel pMOSFET has been reported [1]. However, Ge layers are difficult to integrate with Si due to the misfit between the crystalline lattice parameters and the mismatch of the coefficient of thermal expansions (CTE). Low temperature direct wafer bonding is attractive as an alternative method for allowing the integration of latticemismatched materials. Moreover the wafer bonding technique are specifically sought to allow for the hybrid integration of optoelectronic integrated circuit such as vertical-cavity surface-emitting laser (VCSEL) [2]. We have reported the feasibility of transferring hydrogenimplanted germanium to silicon with a reduced thermal budget is investigated [3]. Based on the low thermal budget exfoliation (Smart-Cut) technique, we investigate the possibility of hybrid pattern stamping for heterogeneous integration. In the experiment hydrogen implanted Ge wafers were bonded directly to oxidized Si using radical activation technique. Prior to bonding, the Ge and oxidized Si wafers were cleaned in an SC1equivalent solution with ozone for Si and without ozone for Ge. After loading into the bonder wafers were activated and bonded in-situ under a pressure of 1kN applied for 5 minutes at a chamber pressure of 10 mbar. The wafers were annealed in-situ at 100°C for 1 hour with an applied pressure of 500N in vacuum followed by an ex-situ anneal at 130°C for 24 hours and additionally 300°C for several minutes. After two-step anneal thin Ge layer transferred on oxideized Si wafer. Bonded interfaces were imaged by SAM. Then implanted Ge with 500um pitch pattern was directly bonded to oxidized Si wafer using oxygen radical activation technique. Figure 1 illustrates the germanium layer was transferred to the host silicon wafer without interface degradation after 300°C short time anneal. It shows that the bond strength of oxygen radical activated sample was high enough to allow pattern stamping in donor germanium wafer after 130°C long time anneal. The successful pattern stamping from a donor germanium to a host silicon wafer has been demonstrated. Figure 2 shows that patterned substrate can be successfully transferred at low temperature, which can be used alignment mark for additional stamping using IR alignment. This low temperature process is suitable for heterogeneous integration for hybrid CMOS platform or hetro-optoelectronics. Fig. 1. Buried interfaces after layer transfer.

Chemical Reactions and Mechanical Properties of the Directly Bonded Ge‐Si Interface

In this study, chemical reactions and mechanical properties of directly bonded Ge‐Si interfaces are investigated. The Ge‐Si bonded interface has been systematically characterized as a function of the thermal budget (200 °C and 300 °C), which demonstrated that the formation of a thin GeO2 cap layer by radical pre‐treatment can reduce the generation rate of voids at the bonded interface significantly. Patterning of one of the wafers prior to bonding can help to achieve high bonding quality thanks to enhanced out‐diffusion of reaction by‐products and stress reduction at the bonded interface. Both numerical modeling and structural analysis show that the presence of diffusion path (channels) at the bonded interfaces result in a maximum bond strength and minimum stress at the bonded interface.