Kian Ann Ng

A Compact, Low Input Capacitance Neural Recording Amplifier

Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 μm CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 mm2. It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 μW, it has an input referred noise of 13.3 μVrms over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated.

Implantable neurotechnologies: a review of integrated circuit neural amplifiers

Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

A Low-Power, High CMRR Neural Amplifier System Employing CMOS Inverter-Based OTAs With CMFB Through Supply Rails

Multichannel neural amplifiers are commonly implemented with a shared reference whose input impedance is several times lower than that of the corresponding signal inputs. This huge impedance mismatch significantly degrades the total common mode rejection ratio (TCMRR) regardless of the amplifiers intrinsic CMRR (ICMRR). This study reports a multichannel neural amplifier system that eliminates this impedance mismatch problem by using single-ended CMOS-inverter-based preamplifiers for both the reference and signal inputs. A common-mode feedback (CMFB) loop through the supply rails of the preamplifiers is implemented to enhance their ac input common mode range to 220 mVpp and their ICMRR to more than 90 dB at low frequencies. The ICMRR is maintained above 80 dB up to 1 kHz by minimizing the load drive mismatch between the signal and reference preamplifiers. Implemented in a CMOS 65 nm process, this 16-channel amplifier system operates at 1 V and consumes 118 μW. It has input referred noise of 4.13 μVrms, leading to a noise efficiency factor (NEF) and a power efficiency factor (PEF) of 3.19 and 10.17, respectively. In vivo recordings of cortical neurons of a macaque were successfully acquired, demonstrating the ability of the amplifier to acquire neural signals in an unshielded environment.

A Bionic Neural Link for peripheral nerve repair

Peripheral nerve injuries with large gaps and long nerve regrowth paths are difficult to repair using existing surgical techniques, due to nerve degeneration and muscle atrophy. This paper proposes a Bionic Neural Link (BNL) as an alternative way for peripheral nerve repair. The concept of the BNL is described, along with the hypothetical benefits. A prototype monolithic single channel BNL has been developed, which consists of 16 neural recording channels and one stimulation channel, and is implemented in a 0.35-μm CMOS technology. The BNL has been tested in in-vivo animal experiments. Full function of the BNL chip has been demonstrated.

An inductively powered CMOS multichannel bionic neural link for peripheral nerve function restoration

This paper describes a inductively powered multichannel bionic neural link (BNL) system-on-chip (SOC) for peripheral nerve function restoration. The BNL-SOC consists of 8 neural recording and 4 stimulation channels, and is implemented in a 0.35-μm CMOS technology. Full function of the BNL has been demonstrated with in-vivo animal experiments. The entire BNL SOC consumes 1.5mW and operates under a 3V supply with an external +/-9V multichannel stimulation output driver.

11.6 A multi-channel neural-recording amplifier system with 90dB CMRR employing CMOS-inverter-based OTAs with CMFB through supply rails in 65nm CMOS

In addition to minimizing input-referred noise and lowering power consumption, a good multi-channel neural amplifier system should be able to significantly reject common-mode electrical interference (CMI). The dominant source of CMI comes from capacitive coupling of electrical mains supply line or EMGs onto neural tissues and can be as high as 100mVpp. Thus any neural recording setup needs a total common-mode rejection ratio (TCMRR) of at least 70dB for a minimum detectable neural signal of 5uVrms. However, multi-channel neural amplifiers are commonly implemented with a shared reference input whose input impedance is several times lower than that of corresponding signal inputs. This results in a large mismatch at the bipolar electrode-amplifier input interface. As analysed in Fig. 11.6.1, the TCMRR is significantly degraded below 70dB, independent of an amplifiers intrinsic CMRR (ICMRR). In this work, we report a micro-power, low-noise 16-channel neural amplifier that eliminates this impedance mismatch problem by using single-ended CMOS inverter-based LNAs for both the reference and signal inputs. Compared to conventional replica channel works, when operating at 1V supply, the LNAs can accommodate a large input CMI of up to 220mVpp through the use of a common-mode feedback (CMFB) loop implemented through the supply rails of the CMOS-inverter-based LNAs, which coincidentally leads to a high amplifier ICMRR.

Neural prosthesis for motor function restoration in upper limb extremity

Restoration of motor function in cases of peripheral nerve injury is a challenging problem. Although peripheral nerves do regenerate, the time required for peripheral nerves to regenerate often causes atrophy to occur in the muscles before they can be re-innervated. This paper presents a solution through proximal recording of nerve signals and distal muscle stimulation. A fully implantable hardware architecture is described that can be operated by means of inductive power and MICS band data transmission schemes. Preliminary experiments and validation studies are reported with non-human primates based on recordings in the median nerve, stimulation of hand muscles, and task decoding and classification. This approach shows promise in creating a neural prosthesis capable of restoring hand movements in patients with upper limb peripheral nerve injuries.

Self-organization of "fibro-axonal" composite tissue around unmodified metallic micro-electrodes can form a functioning interface with a peripheral nerve: A new direction for creating long-term neural interfaces.

A long‐term peripheral neural interface is an area of intense research. The use of electrode interfaces is limited by the biological response to the electrode material.

A 1-V 9.8-ENOB 100-kS/s single-ended SAR ADC with symmetrical DAC switching technique for neural signal acquisition

This paper reports a high-performance low-power and area-efficient single-ended SAR ADC for neural signal acquisition. The proposed 10-bit ADC features a novel symmetrical DAC switching technique that resolves the signal-dependent comparator offset voltage problem in conventional single-ended SAR ADCs, and improves the ADCs ENOB. Combined with an existing LSB single-sided switching method, the proposed switching scheme reduces DAC switching energy by 92% and capacitor array area by 50%. Besides, the proposed ADC also eliminates the need for any power consuming Vcm generation circuit, making it more suitable for low-power System-on-Chip (SoC) integration. The 10-bit prototype ADC is fabricated in a standard 0.18-um CMOS technology. Operating at 1.0 V power supply and 100 kS/s, the proposed ADC achieves 58.83 dB SNDR and 63.6 dB SFDR for a 49.06 kHz input signal. The maximum ENOB is 9.8-bit for low frequency input signal; and the minimum ENOB is 9.48-bit at the Nyquist input frequency. The average power consumption is 1.72 μW and the fig re-of-merit (FoM) is 24.1 fJ/conversion-step.

An intrafascicular electrode with integrated amplifiers for peripheral nerve recording

Thin-film longitudinal intrafascicular electrodes (tf-LIFE) are widely used for peripheral nerve recordings. tf-LIFEs are also promising electrodes for neural signal acquisition in future peripheral nerve prostheses. However, common mode signal interference, and electrical artifacts originating from long wire leads and wire movement are known problems encountered when using such electrodes, which lead to degradation in the recording quality. Here, we report an active tf-LIFE electrode implemented by integrating a neural amplifier chip die in close proximity to a tf-LIFE electrode. Consuming only 1mW and measuring 37 mm×7.2 mm×2.4 mm, this active tf-LIFE electrode creates a reliable connection and considerably shortens the distance between the electrode site and neural amplifier. This active electrode has demonstrated repeatable in-vivo recordings of compound action potentials from the rat sciatic nerve. Our results show that this electrode is suitable for repeated in-vivo recordings of compound action potentials from nerves in applications such as peripheral and visceral nerve interfaces that require low-noise stable nerve recordings.