Yong Ping Xu

A CMOS Carrier-less UWB Transceiver for WPAN Applications

A carrier-less impulse-based UWB transceiver (TRX) chipset is presented. The TRX employs high-order pulse transmission with analog pulse-position modulation. Realized in a 0.18mum CMOS process, the TRX achieves a NF in the range of 7.7 to 8.1dB, an IIP3 of -12.3dBm, and a sensitivity of -80 to -72dBm. It consumes 76mW and 81 mW from a 1.8V supply in transmit and receive modes, respectively

A CMOS VGA With DC Offset Cancellation for Direct-Conversion Receivers

A CMOS dB-linear variable gain amplifier (VGA) with a novel I/Q tuning loop for dc-offset cancellation is presented. The CMOS dB-linear VGA provides a variable gain of 60 dB while maintaining its 3-dB bandwidth greater than 2.5 MHz. A novel exponential circuit is proposed to obtain the dB-linear gain control characteristics. Nonideal effects on dB linearity are analyzed and the methods for improvement are suggested. A varying-bandwidth LPF is employed to achieve fast settling. The chip is fabricated in a 0.35-mum CMOS technology and the measurement results demonstrate the good dB linearity of the proposed VGA and show that the tuning loop can effectively remove dc offset and suppress I/Q mismatch effects simultaneously.

A low power noncoherent CMOS UWB transceiver ICs

A fully integrated pulse based UWB transmitter and receiver (TRX) using a novel and simple noncoherent architecture is presented. Fabricated in a 0.18/spl mu/m CMOS process, the signal from the transmitter is binary amplitude modulated pulses and meets FCC UWB low frequency band (3.1-5 GHz) specification. The receiver archives a noise figure of 7.5 dB, IIP3 of -14 dBm, and sensitivity of -72 dBm. The TRX can attain a transmission rate up to 50 Mbps without synchronization circuits and consumes 41.4 mW average power.

A CMOS Readout Circuit for SOI Resonant Accelerometer With 4-

A fully differential CMOS readout circuit for SOI resonant accelerometer is reported. The readout circuit is essentially an oscillator, consisting of an oscillator and a low noise automatic amplitude control (AAC) loop. A differential sense resonator is proposed to facilitate fully differential circuit topology and improves the SNR under a 3.3-V supply. A second-order AAC loop filter and a novel chopper stabilized rectifier are employed in the AAC loop to remove the noises, in particular, the 1/f noise, and to minimize the phase noise caused by the amplitude stiffening effect. The strong driving feedthrough is avoided by separating the drive and sense operation in the time domain, while using the same electrodes. The complete resonant accelerometer operates under a 3.3-V supply and achieves 140-Hz/g scaling factor, 20 mug/radicHz resolution and 4 mug bias stability. The readout circuit draws 7 mA under 3.3-V supply.

\mu \rm g

Conventional capacitively coupled neural recording amplifiers often present a large input load capacitance to the neural signal source and hence take up large circuit area. They suffer due to the unavoidable trade-off between the input capacitance and chip area versus the amplifier gain. In this work, this trade-off is relaxed by replacing the single feedback capacitor with a clamped T-capacitor network. With this simple modification, the proposed amplifier can achieve the same mid-band gain with less input capacitance, resulting in a higher input impedance and a smaller silicon area. Prototype neural recording amplifiers based on this proposal were fabricated in 0.35 μm CMOS, and their performance is reported. The amplifiers occupy smaller area and have lower input loading capacitance compared to conventional neural amplifiers. One of the proposed amplifiers occupies merely 0.056 mm2. It achieves 38.1-dB mid-band gain with 1.6 pF input capacitance, and hence has an effective feedback capacitance of 20 fF. Consuming 6 μW, it has an input referred noise of 13.3 μVrms over 8.5 kHz bandwidth and NEF of 7.87. In-vivo recordings from animal experiments are also demonstrated.

Bias Stability and 20-

An integrated pulse based ultra-wideband (UWB) receiver using a coherent architecture is presented. BPSK modulation of monocycle Gaussian pulses which meet FCCs UWB frequency band (3.1 - 10.6 GHz) is adopted. The received pulses are correlated with template pulses from a local pulse generator. In each period the correlation value is either sampled by a high speed ADC for further signal processing or sent to a comparator to recover the transmitted data. Simulation and primary measurement results show that the receiver can achieve a demodulation rate of 100/220/480 Mbps and consumes 99 mW peak power. The design is based on a 0.18-/spl mu/m CMOS process.

\mu\rm g/\sqrt{{\hbox{Hz}}}

A 433-MHz OOK transmitter with adaptable data rate is presented. The proposed circuit completely turns off the transmitter during the transmission of dasia0psila and employs a speed-up scheme to obtain high data rates and low wake up time. The data rate can be adjusted and adapted to the need of applications. Realized in 0.35-mum CMOS technology, the OOK transmitter has a measured output power of -12.7 dBm with a dc power consumption pf 560 muW under a 1-V power supply, and a data rate of 3 Mb/s, yielding an energy efficiency of 187 pJ/bit or 3.48 nJ/bit/mW if normalized to the transmitting power. When the proposed speed-up circuitry is enabled, data rate increases to 10 Mb/s, with a dc power consumption of 518 muW achieving a energy efficiency of 52 pJ/bit or 0.97 nJ/bit/mW when normalized.

Resolution

For integrated radio-frequency applications, tunable magnetic inductors are expected. A tunable magnetic inductor, based on magnetoimpedance effect, is presented in this paper. The proposed inductor is constructed with a magnetic inductor body, wound by an insulated coil, inducing a longitudinal dc bias magnetic field when a dc control current is flowing through. Formed by a conductive core coated by a high-permeability magnetic layer, the magnetic inductor body can be realized by either a thin-film structure or a composite wire. The reluctance models for both thin-film and composite wire structures are studied. A prototype tunable magnetic inductor, using a composite wire element, has been characterized. The results show that by varying the dc control current, the inductance L of the magnetic inductor can be tuned. The tunable range depends on the frequency of the current flowing through the inductor. A relative variation of inductance /spl Delta/L/L/sub 0/, up to 18% at low frequency (around 5 MHz), is achieved by applying a bias current of magnitude merely up to 15 mA. The quality factor varies from 5 to 17 in the measured frequency range. The proposed tunable inductor may be further optimized for high-frequency applications and has the potential to be realized in micro-electromechanical systems technology.

A Compact, Low Input Capacitance Neural Recording Amplifier

This paper presents a new phase-noise model for nonlinear microelectromechanical-system (MEMS) oscillators. Two widely recognized existing phase-noise models, namely, the linear time-invariant and time-variant models, are first reviewed, and their limitations on nonlinear MEMS oscillators are examined. A new phase-noise model for nonlinear MEMS oscillators is proposed according to the state-space theory. From this model, a closed-form phase-noise expression that relates the circuit and device parameters with the oscillator phase noise is derived and, hence, can be used to guide the oscillator design. The analysis also shows that, despite the nonlinearity in the MEMS resonator, the phase noise is still governed by its linear transfer function. This finding encourages the designers to operate the MEMS resonator far beyond its Duffing bifurcation point to maximize the oscillation signal power and put more emphasis on the low-noise automatic-amplitude-control-loop design to minimize the noise aliasing through amplitude-stiffening effect without concerning the nonlinear chaotic behavior.

A coherent ultra-wideband receiver IC system for WPAN application

This paper describes a fifth-order multibit low-pass delta-sigma modulator employing a proposed noise-shaping dynamic element matching (NS-DEM) technique to remove DAC nonlinearity error. Unlike most existing DEMs that trade SNR for SFDR, the proposed technique improves both SFDR and SNR. The noise shaping is incorporated in the first integrator of the loop filter without any additional analog circuitry. The fabricated modulator chip achieves 94-dB SFDR and 78-dB DR in 2.2-MHz BW and meets the ADSL2+ specifications.