Kiarash Amiri

WARP, a Unified Wireless Network Testbed for Education and Research

In this paper, we introduce the wireless open-access research platform (WARP) developed at CMC lab, Rice University. WARP provides a scalable and configurable platform mainly designed to prototype wireless communication algorithms for educational and research oriented applications. Its programmability and flexibility makes it easy to implement various physical and network layer protocols and standards. Moreover, the online open-access WARP repository is used to document and share different wireless architectures and cross-layer designs developed at educational and research centers. This repository is a fast and easy solution for students and researchers with a wide range of backgrounds in hardware implementation and algorithm development to collaborate and initiate multi-disciplinary system designs.

Adaptive codebook for beamforming in limited feedback MIMO systems

We propose a new scheme for limited feedback in MIMO systems. We consider transmit beamforming and receiver maximal ratio combining as a base for our work, and propose a novel beamforming codebook to exploit the inherent correlation of the channel. This novel beamforming codebook, unlike the conventional beamforming codebooks, adaptively changes with the channel matrix. Moreover, the adaptive approach is independent of the channel model and can be applied to any general MIMO channel with temporal and spatial correlations. Simulation results show that compared to previously known beamforming schemes, this technique significantly improves the BER performance in spatio-temporally correlated channels.

Architectures for cognitive radio testbeds and demonstrators — An overview

Wireless communication standards are developed at an ever-increasing rate of pace, and significant amounts of effort is put into research for new communication methods and concepts. On the physical layer, such topics include MIMO, cooperative communication, and error control coding, whereas research on the medium access layer includes link control, network topology, and cognitive radio. At the same time, implementations are moving from traditional fixed hardware architectures towards software, allowing more efficient development. Today, field-programmable gate arrays (FPGAs) and regular desktop computers are fast enough to handle complete baseband processing chains, and there are several platforms, both open-source and commercial, providing such solutions. The aims of this paper is to give an overview of five of the available platforms and their characteristics, and compare the features and performance measures of the different systems.

Novel Sort-Free Detector with Modified Real-Valued Decomposition (M-RVD) Ordering in MIMO Systems

K-best MIMO detection technique is the prominent method of simplifying the detection complexity in MIMO systems while maintaining BER performance comparable with the optimum maximum-likelihood (ML) detection technique. However, sorting the candidate nodes in the tree search of the conventional K-best detection can take a significant number of cycles which would reduce the achievable data rate of the detector. In order to reduce this delay, and keep high performance at the same time, we propose using a novel sort-free based MIMO detector which avoids the demanding sorting step. Moreover, this detector utilizes a novel modified real-valued decomposition (M-RVD) ordering that, when compared to the conventional real valued decomposition scheme, can improve the BER performance at no extra computational cost. We show that our proposed detector can outperform the conventional K-best detector with a smaller combination of computation and latency requirements.

FPGA Implementation of Dynamic Threshold Sphere Detection for MIMO Systems

In this paper, we consider the FPGA implementation of a modified sphere detection algorithm. We analyze breadth-first and depth-first search in sphere detection, and compare the relative performance and complexity. Based on these comparisons, we propose a more efficient and less complex scheme, dynamic threshold sphere detection (DTSD), which can effectively increase the throughput and reduce the error rate. We, then, propose a novel architecture for this scheme, and discuss the complexity reduction techniques that we utilized. These techniques do not compromise the overall performance. Finally, the high throughput FPGA implementation results of this algorithm will be presented.

FPGA prototyping of a high data rate LTE uplink baseband receiver

The Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) standard is becoming the appropriate choice to pave the way for the next generation wireless and cellular standards. While the popular OFDM technique has been adopted and implemented in previous standards and also in the LTE downlink, it suffers from high peak-to-average-power ratio (PAPR). High PAPR requires more sophisticated power amplifiers (PAs) in the handsets and would result in lower efficiency PAs. In order to combat such effects, the LTE uplink choice of transmission is the novel Single Carrier Frequency Division Multiple Access (SC-FDMA) scheme which has lower PAPR due to its inherent signal structure. While reducing the PAPR, the SC-FDMA requires a more complicated detector structure in the base station for multi-antenna and multi-user scenarios. Since the multi-antenna and multi-user scenarios are critical parts of the LTE standard to deliver high performance and data rate, it is important to design novel architectures to ensure high reliability and data rate in the receiver. In this paper, we propose a flexible architecture of a high data rate LTE uplink receiver with multiple receive antennas and implemented a single FPGA prototype of this architecture. The architecture is verified on the WARPLab (a software defined radio platform based on Rice Wireless Open-access Research Platform) and tested in the real over-the-air indoor channel.

Cooperative Partial Detection Using MIMO Relays

Using multiple-input multiple-output (MIMO) relays in cooperative communication improves the data rate and reliability of the communication. The MIMO transmission, however, requires considerable resources for the detection in the relay. In particular, if a full detect-and-forward (FDF) strategy is employed, the relay needs to spend considerable resources to perform the full MIMO detection. We propose a novel cooperative partial detection (CPD) strategy to partition the detection task between the relay and the destination. CPD modifies the tree traversal of the tree-based sphere detectors in a way where there is no need to visit all the levels of the tree and only a subset of the levels; thus, a subset of the transmitted streams are visited. The destination, then, combines the source signal and the partial relay signal to perform the final detection step and recover the transmitted vector. We study and compare the performance and complexity of FDF and CPD and show that by using the CPD approach, the relay can avoid the considerable overhead of MIMO detection while helping the source-destination link to improve its performance. More specifically, in the case of a 4 × 4 system, the relay complexity can be reduced by up to 80% of the conventional relaying scheme.

Physical layer algorithm and hardware verification of MIMO relays using cooperative partial detection

Cooperative communication with multi-antenna relays can significantly increase the reliability and speed. However, cooperative MIMO detection would impose considerable complexity overhead onto the relay if a full detect-and-forward (FDF) strategy is employed. In order to address this challenge, we propose a novel cooperative partial detection (CPD) strategy to partition the detection task between the relay and the destination. CPD utilizes the inherent structure of the tree-based sphere detectors, and modifies the tree traversal so that instead of visiting all the levels of the tree, only a subset of the levels, thus a subset of the transmitted streams, are visited. Based on this methodology, the destination combines the source signal and the partial relay signal to perform the detection step. We show, in both simulation and hardware verification on the WARP platform, that using the CPD approach, the relay can avoid the considerable overhead of MIMO detection while helping the source-destination link to improve its performance.

Architecture and Algorithm for a Stochastic Soft-output MIMO Detector

In this paper, we propose a novel architecture for a soft-output stochastic detector in multiple-input, multiple-output (MIMO) systems. The stochastic properties of this detector are studied and derived in this work, and several complexity reduction techniques are proposed to significantly reduce its cost from an architecture-implementation perspective. We also propose an efficient architecture to implement this detector. Finally, this detector is incorporated into an iterative detection-decoding structure, and through simulations, it is shown that the overall frame error rate (FER) performance and complexity is of the same order as that of the conventional K-best sphere detector.

Design and architecture of spatial multiplexing MIMO decoders for FPGAs

Spatial multiplexing multiple-input-multiple-output (MIMO) communication systems have recently drawn significant attention as a means to achieve tremendous gains in wireless system capacity and link reliability. The optimal hard decision detection for MIMO wireless systems is the maximum likelihood (ML) detector. ML detection is attractive due to its superior performance (in terms of BER). However, direct implementation grows exponentially with the number of antennas and the modulation scheme, making its ASIC or FPGA implementation infeasible for all but low-density modulation schemes using a small number of antennas. Sphere decoding (SD) solves the ML detection problem in a computationally efficient manner. However, even with this complexity reduction, real-time implementation on a DSP processor is generally not feasible and high-performance parallel computing platforms such as FPGAs are increasingly being employed for this class of applications. The sphere detection problem affords many opportunities for algorithm and micro-architecture optimizations and tradeoffs. This paper provides an overview of techniques to simplify and minimize FPGA resource utilization of sphere detectors for high-performance low-latency systems.