Kimihiro Ogawa

VCO jitter simulation and its comparison with measurement

We have simulated the phase noise of a voltage controlled oscillator (VCO) using an RF circuit simulator, SpectreRF/sup TM/. This simulator uses a variation of the periodic noise analysis first proposed by Okumura, et al (1993). It computes the power spectral density of the noise as a function of frequency. By assuming that only white noise sources are present in the oscillator, it is possible to derive a simple relationship between the level of the phase noise and the jitter. This excludes flicker noise from consideration, however, since flicker noise is a low-frequency phenomenon, excluding it only affects the accuracy of the long-term jitter. We compared the jitter with measurement and found the error to be less than 2 dB. An AHDL model for the VCO that efficiently exhibits jitter in the time domain is included. The model was written in Verilog-A. This model can be used to determine the affect of VCO jitter on a larger system, such as a phase-locked loop (PLL).

Path Delay Analysis for Hierarchical Building Block Layout System

This paper describes a path delay analysis system which employs an accurate signal delay calculation method for MOS LSIs, taking poly resistance into account. The system takes mask patterns generated by a hierarchical building block layout system as inputs, and verifies timing margins of a large scale random logic LSI in a module-wise bottom up fashion. Path delay analysis using a critical path trace algorithm and an enumerative path trace algorithm in combination is effective in locating critical timing regions in a chip and in analyzing critical paths in the regions in detail.

Analysis of communication circuits based on multidimensional Fourier transformation

There are many communication circuits driven by multitone signals such as modulators and mixers, and so on. In this case, if frequency components of the modulators are largely different, the brute force numerical integration will take an enormous computation time to get the steady-state responses, because the step size must be chosen depending on the highest frequency input. The same situation happens to mixer circuits which generate very low frequency output. In this paper, an efficient algorithm is shown to solve the communication circuits driven by multitone signals which is based on the frequency-domain relaxation method and the multi-dimensional Fourier transformation. Attenuation of the transient phenomena mainly depends on the reactive elements such as capacitors and inductors, so that we partition the circuit into two groups of the nonlinear resistive subnetworks and the reactive elements using the substitution sources. The steady-state response can he calculated in such a manner that the responses at each partitioning point have the same waveform. We have developed a simple simulator carrying out our algorithm that only uses the transient, dc-analysis and ac-analysis of SPICE. It can be easily applied to relatively large scale integrated circuits, efficiently, We found from many simulation results that the convergence ratio at the iteration of our relaxation method is sufficiently large, and can be applied to wide class of the communication circuits.

Estimation of peak current through CMOS VLSI circuit supply lines

We present a new approach for estimating the maximum instantaneous current through the power supply lines of CMOS VLSI circuits. Our final goal is to determine the peak currents and voltage drops through power supply lines of real VLSI circuits within a practical time. Our approach is based on the iMax algorithm of estimating the upper bound of the current, and uses an improved timed ATPG-based algorithm to obtain a tight lower bound. In order to handle sequential circuits, we equate latch outputs with primary inputs for the upper bound estimation and use a logic simulator to determine the initial values for the lower bound estimation. Based on the information obtained, we model all blocks in the circuit as voltage-controlled current sources, with the analog hardware description language (AHDL). After extracting parasitic resistances of the power supply lines, we simulate the entire circuit using an analog simulator and obtain the maximum current estimation and voltage drops in the supply lines. In the modeling procedure we take the negative feedback influence into consideration such that the estimated current reflects a real switching transition. We have implemented the theoretically modeled negative feedback influence into our simulator called PANGI. Some experimental results of applying PANGI to the circuits which consist of more than 1M gates prove the accuracy and reliability of our approach.

Intermodulation analysis of mixer circuits based on frequency domain relaxation method

There are many communication circuits driven by multi-tone signals such as modulators and mixers. If the output frequency components are largely different to each other, the brute force numerical method will take an enormous computation time to calculate the steady-state responses, because the total period becomes very long. In this paper, we show a SPICE oriented algorithm based on the frequency domain relaxation method which can be efficiently applied to relatively large scale ICs.

Stochastic interpolation model scheme for statistical circuit design

In this paper, a stochastic interpolation model (SIM) scheme is proposed to approximate circuit performances for statistical circuit design purpose. First, a parameter estimation technique for SIM construction is presented. Next, a sequential sampling strategy based on variance analysis is described to efficiently fit SIM with the least amount of sample data. Finally, the coefficient of variance is introduced as a new criterion for approximation accuracy check. The effectiveness of presented implementation scheme is demonstrated by several numerical examples as well as a statistical circuit analysis example.<<ETX>>

Path delay analysis for hierarchical building block layout systems

This paper describes a path delay analysis system which employs an accurate signal delay calculation method for MOS LSIs, taking poly resistance into account. The system takes mask patterns generated by a hierarchical building block layout system as inputs, and verifies timing margins of a large scale random logic LSI in a module-wise bottom up fashion. Path delay analysis using a critical path trace algorithm and an enumerative path trace algorithm in combination is effective in locating critical timing regions in a chip and in analyzing critical paths in the regions in detail.