Kimimori Hamada

A Fast Loss and Temperature Simulation Method for Power Converters, Part I: Electrothermal Modeling and Validation

Simulation of power converters has traditionally been carried out using simplified models to shorten simulation time. This will compromise the accuracy of the results. A proposed fast simulation method for simulating converter losses and device temperatures over long mission profiles (load cycles) is described in this paper. It utilizes accurate physics-based models for the device losses, and is validated with experimentally obtained results.

A Fast Loss and Temperature Simulation Method for Power Converters, Part II: 3-D Thermal Model of Power Module

This paper describes the development and implementation of an analytical 3-D thermal model for fast and accurate thermal simulation of power device modules in electrothermal converter simulation. A Fourier-based solution is used to solve the 3-D heat equation. The solution can describe the variation of temperature through the whole inverter power module structure as a function of time. The model can simulate thermal interactions resulting from multiple heat sources. The thermal model is extremely fast to simulate compared to finite-element (FEM) approaches. The new model has been implemented in MATLAB/Simulink in order to cosimulate with the converter model which is in the same form. The model has been validated against the computational fluid dynamics (CFD) software package FLOTHERM and shows good agreement. The required aspects of 3-D heat diffusion are captured successfully by the Fourier-based model.

SiC—Emerging Power Device Technology for Next-Generation Electrically Powered Environmentally Friendly Vehicles

The automotive industry is developing a range of electrically powered environmentally friendly vehicles such as hybrid vehicles (HVs), plug-in hybrid vehicles, full electric vehicles, and fuel cell vehicles to help reduce tailpipe CO2 emissions and achieve energy diversification. HVs are regarded as one of the most practical types of environmentally friendly vehicle and have already been widely accepted in the market. Toyota Motor Corporation has positioned HV systems as a core technology that can be applied to all next-generation electrically powered environmentally friendly vehicles and is currently working to enhance the performance of HV system components. Because of its low loss and high-temperature operation properties, silicon carbide (SiC) is regarded as a highly promising material for power semiconductor devices to help reduce the size and weight of the power control unit, one of the key components of a HV system. Wide-ranging activities are under way to meet the challenges of adopting SiC in an automotive environment, such as the development of crystal growth technologies, device structures, process technologies, defect analysis, and application to on-board systems. This paper describes the current situation and future prospects for on-board SiC power devices and the development of SiC-based technologies.

Relationship between threading dislocation and leakage current in 4H-SiC diodes

The impact of threading dislocation density on the leakage current of reverse current-voltage (I–V) characteristics in Schottky barrier diodes (SBDs), junction barrier Schottky diodes, and p-n junction diodes (PNDs) was investigated. The leakage current density and threading dislocation density have different positive correlations in each type of diode. Consequently, the correlation in SBDs is strong but weak in PNDs. Nano-scale inverted cone pits were observed at the Schottky junction interface, and it was found that leakage current increases in these diodes due to the concentration of electric fields at the peaks of the pits. The threading dislocations were found to be in the same location as the current leakage points in the SBDs but not in the PNDs.

Wide-voltage SOI-BiCDMOS technology for high-temperature automotive applications

This paper describes a new wide-voltage SOI-BiCDMOS technology for high-temperature automotive applications. This technology is capable of integrating 35V, 60V, and 80V Nch and Pch LDMOS, 35V BJT, and 6V CMOS devices on a single chip. The devices are completely isolated dielectrically using both deep trench isolation (DTI) and a buried oxide (BOX) layer in a silicon-on-insulator (SOI) wafer for stable operation at high temperatures up to 175°C. The devices were developed using a 0.35μm process. In particular, the LDMOS devices have achieved competitive levels of low Ron∗ A and good SOA.

Impact of surface morphology above threading dislocations on leakage current in 4H-SiC diodes

The nano-scale pits above the threading dislocations were found to be in the same location as the leakage current points in Schottky barrier diodes and junction barrier Schottky diodes. This study compared the leakage current of 1.2 kV, 200 A diodes with and without nano-scale pits. The leakage current in diodes without nano-scale pits was lower than those in diodes with pits. In the diodes without nano-scale pits, the leakage currents were generated at step-bunching area and the leakage current at the threading dislocations was not observed.

Novel Electro-Thermal Coupling Simulation Technique for Dynamic Analysis of HV (Hybrid Vehicle) Inverter

This paper describes a novel electro-thermal coupling simulation technique mainly focused on the dynamic analysis of the HV inverter during WOT (Wide Open Throttle) operation. This technique can predict the junction temperature of power devices installed within the power module accurately. This simulation technique is composed of an inverter circuit model including power semiconductor device models, a novel compact thermal model suitable for automotive power modules and motor model. Various information and conditions such as motor current, motor rotation speed, switching frequency and variable DC-link voltage are applied to the simulation for carrying out the WOT operation. The comparison between the simulated and measured results indicates that this method offers reasonable accuracy for the IGBT temperature estimation where the worst case error in the IGBT temperature is less than 10 deg-C. It takes 210 min to complete the WOT simulation with duration of 4 seconds.

Detection of localized UIS failure on IGBTs with the aid of lock-in thermography

Abstract IGBTs with embedded current monitors, i.e. realized by separating a small part of the main device emitter and using it as the current sense terminal, are currently used to integrate intelligent power modules (IPMs). In a previous paper [Breglio G, Irace A, Napoli E, Spirito P, Hamada K, Nishijima T, et al. Study of a failure mechanism during UIS switching of planar PT-IGBT with current sense cell. Microelectron Reliab 2007;47(9–11):1756–60] we have demonstrated how, during UIS switching in particular circuit configurations, the interplay between the sense-emitter cell and the rest of the device can lead to latch-up of the lateral p–n–p bipolar transistor and current focalization in the sense-emitter cell which finally causes device failure. In this paper, we show how the location of this very localized failure spot can be very accurately determined with the aid of a very sensitive lock-in thermography setup. The main advantage of this approach is the direct applicability to the failed device without the need of time consuming sample preparation as in other failure analysis (FA) techniques.

Investigations on current filamentation of IGBTs under undamped inductive switching conditions

We have investigated current filamentation of IGBTs occurring under UIS (undamped inductive switching) conditions, by using electro-thermal device simulations. In this paper, we present that the formation of a current filament inevitably takes place even if the device active region include no weak spots. In addition, it is clarified that the current filament travels inside the active region with Joule self-heating, and the filament pinning due to parasitic bipolar action at the weak spot leads to lowering UIS capability.

Neutron induced single-event burnout of IGBT

Cosmic-ray neutrons can trigger a single-event burnout (SEB), which is a catastrophic failure mode in power semiconductor devices. It was found experimentally that the incident neutron induced SEB failure rate increases as a function of the applied collector voltage in an insulated gate bipolar transistor (IGBT). Moreover, the failure rate increased sharply with an increase in the applied collector voltage when the voltage exceeded a certain threshold value. Transient device simulation showed that the onset of impact ionization at the n− drift/n+ buffer junction (nn+ junction) can trigger turning-on of the inherent parasitic thyristor, and then SEB subsequently occurs. In addition, it was analytically derived that reducing the current gain of the parasitic transistor was effective in increasing the SEB threshold voltage. Furthermore, ‘white’ neutron-irradiation experiments demonstrated that suppressing the inherent parasitic thyristor action leads to an improvement of the SEB threshold voltage.