Kimo Y. F. Tam

A 12.5-Gb/s self-calibrating linear phase detector-based CDR using 0.18μm SiGe BiCMOS.

A 12.5 Gb/s half-rate clock and data recovery (CDR) circuit is described. The CDR uses a half-rate linear phase detector (LPD) which minimizes the number of latches required. To correct for static phase offsets (SPO) that inevitably result from variations in analog circuit parameters, a calibration scheme is used on startup. Measured high-frequency jitter tolerance is improved by up to 0.2 UIpp through this calibration. Power for the CDR, excluding the PLL and I/O circuits, is 82 mW at 12 Gb/s.

High-speed wireline timing recovery & PLLs

Advances in high-performance clock generator circuits and timing recovery techniques are essential for the continued improvements in performance, power, and area demanded by current and future wireline communication systems. The papers presented in this section highlight developments in timing recovery techniques for ADC-based receivers and burst-mode systems, a new approach to realize PLLs with peaking-free transfer functions, and analysis and design comparisons of capacitor-multiplier and passive loop filters for low-area PLL implementations.