John G. Kenney

Multi-level decision feedback equalization for saturation recording

An impediment to the practical use of fixed-delay tree search with decision feedback (FDTS/DF) for retrieving data from hard disk drives is that four additions and one multiplications must be evaluated in one clock cycle. It is shown here that on recording channels using 2/3

Design of multibit noise-shaping data converters

A synthesis methodology for selecting locations of thez-domain poles for noise-shaping coders that use multibit internal converters is presented. A key aspect of the proposed methodology is the use of the |L|1 norm of the noise transfer function to guarantee stability rather than the power gain or |L|2 norm which is commonly used in the design of 1-bit noise-shaping coders. Simulation verifies that the performance predicted by the new method is within a few dBs of the actual performance. In addition, two hand-designed loop filters from the literature are compared with designs generated by the proposed method.

Multi-level decision feedback equalization: an efficient realization of FDTS/DF

Multi-level decision feedback equalization (MDFE) is a detection technique which achieves equivalent error rate performance to fixed-delay tree search with decision feedback equalization, while using the simpler architecture of decision feedback equalization. The desired equalization target in MDFE is accommodated by a low order IIR filter, thereby suggesting that all of the forward filtering can be done with continuous-time filters. A potentially low power architecture for MDFE will be described which includes circuit considerations for the phase and gain detectors. >

An enhanced slew rate source follower

A unity-gain buffer capable of high slew rates in both the positive and negative directions is presented. By sensing the drain current of the common-drain device in an NMOS source follower, the extent of slewing is detected, and the tail current of the source follower is dynamically adjusted. A buffer incorporating this strategy was implemented in a 2 /spl mu/m p-well process. This buffer has over 4 times the negative-going slew rate and twice the bandwidth of a source follower, while requiring only 13% more static power. Moreover, the output voltage swing range is as large as that of a source follower. With a 20 pF output load, the measured 3-dB bandwidth was 9 MHz. The signal-to-total-harmonic-distortion ratio with 2 V/sub p-p/ sinewave input at a frequency of 2 MHz was better than 50 dB. >

Allpass forward equalizer for decision feedback equalization

An allpass forward equalizer (APFE) for use with decision feedback equalization (DFE) is described, The APFE has poles, unlike the normally implemented FIR (finite impulse response) forward equalizer; equalizers with poles can provide superior performance or reduced hardware complexity when compared to all-zero equalizers, but can have local optima and are more difficult to design. A theoretical basis for the allpass is presented and a systematic design procedure is described. It is shown that there are no local optima in a sufficient region about the global optimum such that adaptation is feasible. A performance vs. complexity advantage is shown for the APFE relative to the FIR forward equalizer, and implementation as a continuous-time filter is proposed.

Geometric representation of the tree-search detector

Fixed-delay tree search with decision feedback (FDTS/DF) has been proposed for retrieving data from hard disk drives. One problem with the algorithm as originally posed is the large number of serial operations that must be performed during one clock cycle. The authors explore the decision space in FDTS/DF using linear discriminants, which leads to a geometric depiction of the decision space. For channels with a d=0 minimum runlength constraint the number of serial computations reduces to one multiplication and one addition. More importantly, though, on high density channels with a d=1 minimum runlength constraint, the detector can be implemented as a multilevel decision feedback equalizer.<<ETX>>

A comparative study of two adaptive continuous-time filters for decision feedback equalization read channels

This paper presents a comparative study of two adaptive continuous-time 3rd order allpass equalizers for magnetic disk decision feedback equalization read channels. These are based on adaptive current-mode Gm-C structures employing low-mismatch high bandwidth pseudo-differential balanced transconductors and polarized MOSFET arrays as integrating capacitors. Transistor level simulation results are presented to demonstrate the performance characteristics of both structures.

Pipelining for speed doubling in MDFE

The data rate in decision feedback detectors is often limited by the time it takes the slicer to make a decision, followed by generating an output value from the decision feedback filter and finally establishing the input of the slicer for the next symbol period. It is shown that the equalized dibit response for multi-level decision feedback equalization can be designed so that the first tap of the feedback filter is 0, thereby allowing the operations of the critical path to be spread over 2 symbol periods. By eliminating the first coefficient of the feedback filter, an architecture which doubles the overall symbol rate by using 2 decision feedback detectors each operating at one-half the symbol rate is realizable. Architectural considerations for determining the error required in the LMS adaptation of the timing, gain and feedback equalizer are described.

A system architecture for multi-level decision feedback equalization

System issues such as clock recovery, automatic gain control and determination of the filter coefficients for both the forward and backward equalizers are examined for multi-level decision feedback equalization (MDFE). A software implementation on 2/3(1,7) RLL coded data stored at a bit density of 1.67 PW50 and retrieved by an MR head demonstrate the implementation of a channel based on MDFE. >

Clock recovery on unequalized magnetic recording channels

As new data recovery schemes based on sampling detectors are devised, a need for quick but exhaustive bit error rate characterization becomes important. Hardware prototypes provide the only practical means by which detection schemes can be evaluated at error rates required in a product. Issues such as clock recovery and automatic gain control are often ignored during the evaluation of detection schemes in software, but loom as important issues when it is time to build the prototype channel. In this paper, a technique for performing gradient based clock recovery on unequalized playback channels will be proposed. This phase detector relies on knowledge of the step response of the channel as well as the stored data. Depending upon the phase margin of the phase-locked loop during tracking mode, this phase detector can also be used in a data driven mode.<<ETX>>