Kinga Marton

Parallel implementation of the NIST Statistical Test Suite

Randomness test suites constitute an essential component within the process of assessing random number generators in view of determining their suitability for a specific application. Evaluating the randomness quality of random numbers sequences produced by a given generator is not an easy task considering that no finite set of statistical tests can assure perfect randomness, instead each test attempts to rule out sequences that show deviation from perfect randomness by means of certain statistical properties. This is the reason why several batteries of statistical tests are applied to increase the confidence in the selected generator. Therefore, in the present context of constantly increasing volumes of random data that need to be tested, special importance has to be given to the performance of the statistical test suites. Our work enrolls in this direction and this paper presents the results on improving the well known NIST Statistical Test Suite (STS) by introducing parallelism and a paradigm shift towards byte processing delivering a design that is more suitable for todays multicore architectures. Experimental results show a very significant speedup of up to 103 times compared to the original version.

Byte-oriented efficient implementation of the NIST statistical test suite

Randomness comes in many flavours and has countless applications in various domains which state different quality requirements for the outcome of random number generators, therefore decisions on the suitability of a randomness generator for a specific application has to be made as a result of thorough analysis including the essential part of statistical testing. But as systems tend to consume increasingly larger volumes of random data, having high throughput random number generators is imperative, but not sufficient, because between generators and the application requiring randomness the data can flow with a speed limited by the performance of the statistical testing units interposed. Furthermore statistical tests can assess only certain features of random sequences based on the statistical properties of true random sequences but can not ensure perfect randomness, hence several statistical tests have to be applied in order to increase the confidence in the selected generator. As a result there is a stringent need for high performance test suites for assessing the quality of the generated random sequences. Our work enrols in this direction presenting a performance efficient version of the well known NIST statistical test suite for random and pseudorandom number generators based on a paradigm shift towards byte stream processing mode inside the tests. Experimental results show significant performance improvements of up to 13 times in average compared to the original version.

Data Flow Entropy Collector

Collecting entropy from various sources available within a regular PC and combining them in an entropy pool is often used as an alternative to pseudo random number generation. Cheaper than using a hardware true random number generator (TRNG), this method offers a good approximation of a TRNG, commonly known as an unpredictable random number generator. The source of unpredictability is ultimately the human-computer interaction that, when complex enough, is irreproducible by an adversary. The present paper proposes a novel approach to combining the entropy from various sources in a data flow manner, thus increasing the degree of unpredictability. The result is a highly unpredictable random number generator, of potentially good quality.

Unpredictable random number generator based on mobile sensors

Cryptographic applications need quality random number generators for reaching a high level of security. As the industry is moving forward at a high pace and the mobile paradigm emerging, new sources of randomness arise. One of them is the new generation of phones, also known as smartphones. We propose an unpredictable random number generator, which, using the hardware sensors of a modern phone, is able to produce high quality sequences of random bits.

Parallel object-oriented implementation of the TestU01 statistical test suites

Evaluation of the randomness quality of a random number generator requires an efficient suite of statistical tests which takes advantage of the processing power of todays multi-core processing power in order to cope with the large amount of data to be processed. While, in theory, most complex processing algorithms can be tuned for concurrent execution, the solution will eventually reach a state in which a compromise needs to be made between the overall performance and the configurability and usability of the application. Our solution is based on completely re-designing the TestU01 architecture to include the notion of parallel computing as part of the general requirements, and not as a tool used for increasing performance. Implementation of this design is done using concepts from the object-oriented paradigm, and uses the .NET Task Parallel Library. Experimental results show that the parallel OOP based implementation of the TestU01 library not only obtains similar results as the previous parallel version, but in some cases a better speedup is obtained.

Parallel implementation of the TestU01 statistical test suite

As the need of high quality random number generators is constantly increasing especially for cryptographic algorithms, the development of high throughput randomness generators has to be combined with the development of high performance statistical test suites. Unfortunately the implementations of the most popular batteries of test suites are not focused on efficiency and high performance, do not benefit of the processing power offered by todays multi-core processors and tend to become bottlenecks in the processing of large volumes of data generated by various random number generators. Hence there is a stringent need for providing highly efficient statistical tests and our research efforts and results on improving and parallelizing the TestU01 test suite intend to fill this need. Experimental results show that the parallel version of TestU01 takes full advantage of the systems available processing power, reducing the execution time up to 4 times on the tested multicore systems.

Unpredictable Random Number Generator Based on Hardware Performance Counters

Originally intended for design evaluation and performance analysis, hardware performance counters (HPCs) enable the monitoring of hardware events, yet are noisy by their very nature. The causes of variations in the counter values are so complex that are nearly impossible to determine. Hence, while being a major issue in the process of accurately evaluating software products, the unpredictability exhibited by HPCs offer a high potential for random number generation. In the present paper we propose a new unpredictable random number generator (URNG) based on HPCs and analyze the feasibility of producing cryptographic quality randomness. The experiments performed on the proposed generator show that the quality and throughput of the new design is comparable to those exhibited by the well known HAVEG URNG [1]. The results of thorough statistical testing prove the high randomness quality of the produced sequences enabling the generator to be considered a suitable candidate for integration in cryptographic applications.

Implementation of cryptographic algorithms on a Grid infrastructure

Cryptographic algorithms are the fundamental building blocks of information security systems and their strength generally relies on the concept of computational complexity. But the process of increasing the computational effort needed by an adversary in order to break the provided security has a dramatic impact on the performance of the cryptographic application and sets a severe limit to the proposed security level due to the computational and data intensive operations which require extensive processing power and storage resources. Our solution is to link cryptography to an architecture specially designed to satisfy these demands, namely Grid computing, which has known an increasing popularity in recent years. The wide majority of cryptographic algorithms are designed sequentially and are not ready to embrace the enhancement brought by advances in parallel and distributed computing technologies and hence can not take the plunge to a higher performance level through parallel execution without a proper adjustment process. This paper presents our results on adjusting and implementing several well known cryptographic algorithms on a Grid infrastructure focusing on the achieved performance improvements.

Parallel ENT - ParENT

As the need for high throughput and good quality random number generators is constantly increasing in security applications, the efforts for developing high performance generators must be combined with increasing the performance of the batteries of statistical tests that assess their quality.In order to increase the confidence in the random number generators, several randomness tests are applied on their output sequences. This can be a very time consuming task, because many large output sequences need to be tested in order to obtain relevant results. Therefore we need fast, efficiently implemented batteries of statistical tests.This paper presents an improved and parallel version of the well known ENT program for testing random number sequences, originally written by John Walker. Experimental results show that our improved and parallel ENT version, ParENT, is very suitable for today’s multicore architectures making better use of the available processing power and reducing the execution time up to 10 times on the tested multicore systems.

Counting bits in parallel

The efficiency of bit counting operations can have a considerable impact on the performance of file systems, databases, machine learning algorithms and information security systems. Recognizing the great importance of bit counting, recent processors provide hardware implementations of dedicated instructions for efficient population counting. We have previously studied the never ending problem of counting bits efficiently, and provided comparative results considering a serial execution model [2]. The current research is a follow-up work aimed to analyze and benchmark different parallel bit counting methods in order to further enhance the performance and harness the processing power of todays multicore systems.