Alin Suciu

Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration

This paper presents the hardware implementation of the widely known NIST Statistical Test Suite – a battery of statistical tests for pseudorandom number generators (PRNGs) and true random number generators (TRNGs) – in a single Xilinx FPGA chip, using dynamic partial reconfiguration. The design offers a basic framework for easy integration of any additional randomness evaluation tests as well. Due to the integration of both the TRNG and the tests suite in a single FPGA chip, our solution offers new opportunities in the area of random number generation and testing, greatly reducing the time between the generation and the validation of the generated sequences of random bits.

Practical Issues in Implementing TRNGs in FPGAs Based on the Ring Oscillator Sampling Method

Field programmable gate arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. For all such systems, random numbers are essential. One of the most well-known methods for producing true random number sequences in FPGAs is based on the phenomenon of jitter and built upon ring oscillators. This paper describes how to overcome the placement sensitivity caused by the different physical properties of the logic elements, thus extending the portability of TRNGs on various FPGA boards. Our design offers an easy implementation, but in the same time maintains the good quality and high generation throughput of random numbers.

Parallel implementation of the NIST Statistical Test Suite

Randomness test suites constitute an essential component within the process of assessing random number generators in view of determining their suitability for a specific application. Evaluating the randomness quality of random numbers sequences produced by a given generator is not an easy task considering that no finite set of statistical tests can assure perfect randomness, instead each test attempts to rule out sequences that show deviation from perfect randomness by means of certain statistical properties. This is the reason why several batteries of statistical tests are applied to increase the confidence in the selected generator. Therefore, in the present context of constantly increasing volumes of random data that need to be tested, special importance has to be given to the performance of the statistical test suites. Our work enrolls in this direction and this paper presents the results on improving the well known NIST Statistical Test Suite (STS) by introducing parallelism and a paradigm shift towards byte processing delivering a design that is more suitable for todays multicore architectures. Experimental results show a very significant speedup of up to 103 times compared to the original version.

Byte-oriented efficient implementation of the NIST statistical test suite

Randomness comes in many flavours and has countless applications in various domains which state different quality requirements for the outcome of random number generators, therefore decisions on the suitability of a randomness generator for a specific application has to be made as a result of thorough analysis including the essential part of statistical testing. But as systems tend to consume increasingly larger volumes of random data, having high throughput random number generators is imperative, but not sufficient, because between generators and the application requiring randomness the data can flow with a speed limited by the performance of the statistical testing units interposed. Furthermore statistical tests can assess only certain features of random sequences based on the statistical properties of true random sequences but can not ensure perfect randomness, hence several statistical tests have to be applied in order to increase the confidence in the selected generator. As a result there is a stringent need for high performance test suites for assessing the quality of the generated random sequences. Our work enrols in this direction presenting a performance efficient version of the well known NIST statistical test suite for random and pseudorandom number generators based on a paradigm shift towards byte stream processing mode inside the tests. Experimental results show significant performance improvements of up to 13 times in average compared to the original version.

FPGA based TRNG using automatic calibration

This paper presents a new method to improve the quality of True Random Number Generators implemented on Field Programmable Gate Arrays. Traditionally implementations require an exact manual calibration to achieve the best performance. In this paper we are suggesting a method which uses modern clocking features to perform automatic calibration. This feature also enable the efficient use of some jitter sources previously unavailable to designers. The present design also uses one of these sources, the jitter available on the clock lines. The implementation has the advantage of a relatively high throughput in a small size. The quality of the generated stream is also high, passing multiple test suites. The implementation is also provided as a calibrating framework which can be easily reused for other designs.

Data Flow Entropy Collector

Collecting entropy from various sources available within a regular PC and combining them in an entropy pool is often used as an alternative to pseudo random number generation. Cheaper than using a hardware true random number generator (TRNG), this method offers a good approximation of a TRNG, commonly known as an unpredictable random number generator. The source of unpredictability is ultimately the human-computer interaction that, when complex enough, is irreproducible by an adversary. The present paper proposes a novel approach to combining the entropy from various sources in a data flow manner, thus increasing the degree of unpredictability. The result is a highly unpredictable random number generator, of potentially good quality.

Simulation-based schedulability tests for multiprocessor real-time systems

The assimilation of multiprocessor programming into the real-time applications domain is limited because there are not enough theoretical and pragmatic tools for proving the feasibility of such systems. Theoretical results are few and tend to be too complex for a practical implementation. In this paper, we combine theoretical analysis results with simulation to obtain a tool, which can assess the multiprocessor real-time schedulability of periodic task sets. We performed simulations on different scenarios in order to determine the features that influence schedulability of a multiprocessor real-time system.

Unpredictable random number generator based on mobile sensors

Cryptographic applications need quality random number generators for reaching a high level of security. As the industry is moving forward at a high pace and the mobile paradigm emerging, new sources of randomness arise. One of them is the new generation of phones, also known as smartphones. We propose an unpredictable random number generator, which, using the hardware sensors of a modern phone, is able to produce high quality sequences of random bits.

Statistical Testing of Random Number Sequences Using Graphics Processing Units

Due to the great processing power available on today’s Graphics Processing Units (GPU), we studied the suitability of mapping statistical testing algorithms to this specialized hardware. Out of the testing algorithms proposed by the National Institute of Standards and Technology (NIST), only some were suitable for implementation on GPU, due to the computational format and restrictions of the hardware. Experimental results show a significant increase in performance; very good acceleration was obtained especially for large amounts of input data. We estimate that both the performance and the categories of testing algorithms suitable for implementation will increase over time, as new GPU generations are developed and made available. In this light, using General Purpose computing on Graphics Processing Units (GPGPU) for testing sequences of random numbers is a viable and promising option for future research.

Statistical testing of random number sequences using CUDA

Previous research in the field of statistical testing of random number sequences using Graphics Processing Units (GPU) [1] has shown that this approach yields a significant increase in performance for a subset of the statistical tests proposed by National Institute of Standards and Technology (NIST) [2]. The present paper aims at further improvements in the performance of statistical testing of random number sequences, by focusing on another technology dedicated to GPU computing, the Compute Unified Device Architecture (CUDA). CUDA extends the C programming language with functionality for massively parallel programming on GPUs. Due to the flexibility given by the CUDA memory and thread model plus the optimizations that take advantage of the Parallel Data Cache, we were able to further improve the performance of the statistical testing algorithms proposed by NIST. Experimental results show speedups of up to 219, depending on the test and the size of the input data, with an overall average speedup of 51.