Kingsuk Maitra

A 0.063 µm 2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE2) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.

Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High-

Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e.,<i>L</i>_GATE ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-first flow. A “long and narrow” fin layout (i.e., fin length ~ 1 μm) was leveraged to preserve uniaxial tensile strain in the transistors. These devices exhibit drive currents suitable for high-performance logic technology. The change in the slope of <i>R</i>_ON - <i>L</i>_GATE (dR_ON/dL_GATE), transconductance <i>G</i>_MSAT, and injection velocity (<i>v</i>_inj) measurements indicate a ~ 15% mobility-induced <i>I</i>_ON enhancement with SSOI relative to SOI nFinFETs at ultrashort gate lengths. Raman measurements conducted on SSOI substrates after fin formation demonstrate the preservation of ~ 1.3-GPa uniaxial tensile strain even after 1100°C annealing.

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In this paper, we investigate the optimization of device layout and embedded source/drain (eS/D) shape profile for strain engineered 22-nm node Si and SiGe p-channel trigate field-effect transistors by finite-element method simulations. A nested trigate layout with dummy gates is found to retain the maximum channel stress for all three conduction planes. The tradeoff between achievable mobility enhancement and active device density for the nested trigate layout is also investigated in this paper. Next, the impact of the eS/D shape on the channel stress for all three conduction planes is studied, and the rounded eS/D shape is found to be the optimal shape contrary to the planar case with sigma-shaped eS/D. Finally, strained SiGe channel trigate transistors are investigated as a potential candidate for future technology nodes. The evolution of formation and relaxation of the average strain of the compressively strained SiGe channel is systematically studied as a function of fin formation, embedded S/D formation, and layout configuration.

/Metal-Gate nFinFETs for High-Performance Logic Applications

A significant increase in parasitic resistance (R<inf>PARA</inf>) fluctuation is observed when S/D length is getting smaller than the characteristic length (L<inf>TRANS</inf>). Resistance change evaluated on double gate finFETs with various fin lengths shows an excellent agreement between the experimental data and the analytical model. Further R<inf>PARA</inf> fluctuation improvement can be realized by optimizing the L<inf>TRANS</inf>.

Layout-Dependent Strain Optimization for p-Channel Trigate Transistors

Hot-carrier degradation (HCI) in aggressively scaled undoped-body devices is carefully studied and compared for high-k/metal gate FINFETs and extremely thin silicon-on-insulator (ETSOI) transistors. We show that HCI involves different degradation mechanisms for silicon-on-insulator (SOI)-FINFETs and ETSOI devices though both are fabricated on undoped body. For FINFETs, the HC degradation correlated with interface trap generation in the channel region, whereas for ETSOI, trap generation and electron trapping in the spacer-nitride region were observed.

Analysis of parasitic resistance in double gate FinFETs with different fin lengths

A methodology based on the transistor body effect is used to monitor inversion oxide thicknesses (Tinvs) in high-κ/metal-gate undoped ultrathin-body short-channel SOI FINFETs. The extracted Tinvs are benchmarked to independent capacitance-voltage (C-V) measurements. For the first time, device simulation is introduced to understand the fundamental difference in Tinv values extracted using the two techniques, which is driven by the inversion charge centroid at different bias conditions.