Kiran George

Design and performance evaluation of a 2.5-GSPS digital receiver

Todays very deep submicron IC technology enables high-performance analog and digital applications to be integrated on a single piece of silicon. For this effort, a design of 2.5 giga-sample per second (GSPS) receiver-on-a-chip (ROC) is presented. For our design, we take advantage of a compensation technique to reduce spurs and improve instantaneous dynamic range. A major goal is to produce a low-cost, small, and lightweight, and low-power ROC. Our design will cover a 1-GHz bandwidth (125 - 1125 MHz), and it will correctly process two simultaneous signals by detecting their frequency, pulsewidth (PW), and time of arrival (TOA). The single or dual signal, spur-free dynamic ranges and two signal instantaneous dynamic ranges of our design are high. The minimum frequency separation of two signals is 10 MHz (one channel width), and the maximum amplitude separation (dynamic range) of two signals is 18 dB with the second signal false alarm less than 1%.

Configurable and Expandable FFT Processor for Wideband Communication

A practical fast Fourier transform (FFT) processor can contain several millions of gates, so effective design techniques usually are required in order to guarantee high-speed products. A look-up table (LUT) methodology is developed and demonstrated on variable length (128-1024 point), variable bit-precision (6-12 b) FFT with uniform bit truncation and optimum bit truncation for wideband digital receiver in radar applications. The FFT processors are designed using a standard 130 nanometer CMOS process and operates down to 120 mV. The required processing time for the non-configurable 12-b 1024-point LUT FFT is 15.78 ns at a clock frequency of 470 MHz. The required time for configurable LUT 12-b 1024-point FFT processing is 61 ns. The configurable LUT FFT processor with short transform lengths can be expandable so that they can be used easily to form new FFT processors with longer transform lengths. The performance comparison of conventional FFT, LUT FFT, and configurable LUT FFT for digital wideband receiver application is discussed.

Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test

A configurable two-dimensional (2-D) LFSR based test generator and an automated synthesis procedure are presented. Without storage of test patterns, a 2-D LFSR based test pattern generator can generate a sequence of precomputed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable faults). The hardware overhead is decreased considerably through configuration. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2-D LSFR can also be adopted in chip-level and system-on-a-chip (SoC) BIST.

Multiple Signal Detection Digital Wideband Receiver using Hardware Accelerators

A three gigasample per second (GSPS) digital wideband receiver that operates in a 1.25-GHz instantaneous bandwidth (IBW) is proposed. In addition to building such systems, offloading of computation-intensive tasks to a combination of specialized hardware accelerators such as graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) to increase the overall receivers dynamic performance is analyzed. The receiver detects up to 15 signals with a maximum attainable instantaneous dynamic range (IDR) of 62.5 dB before the next set of data arrives for processing.

Extension of Two Signal Spur Free Dynamic Range of Wideband Digital Receivers using Kaiser Window and Compensation Method

A technique of using the Kaiser window to reduce the spectral leakage by eliminating the discontinuities at the time window edges and using the compensation method to uncover the weak signal for extension of the two signal spur free dynamic range (SFDR) for wideband digital receivers is presented. The combination of both techniques extends the two signals SFDR of the receiver to 24 db

A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement

As a modern radar receiver must rapidly search a large frequency range with maximum sensitivity, capabilities such as high instantaneous dynamic range (IDR), good multiple-signal-detection capability, wider bandwidth (BW), and high-frequency resolution are indispensable. Many techniques proposed to improve digital wideband receiver performance are computationally intensive and limit their real-time performance due to hardware constraint. In this paper, an innovative three gigasample-per-second hybrid computing platform digital wideband receiver system is presented, which employs two Nvidia Tesla C2050 graphics processor units and a Xilinx Virtex-5 field-programmable gate array for hardware acceleration to drastically improve receiver performance over its predecessor designs. The receiver detects five simultaneous signals in 1.25-GHz BW (125-1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture achieves high-resolution spectral estimation and employs a hardware mechanism for multiple-signal detection before the next set of data arrives for processing.

Multiple Signal Detection and Measurement Using a Configurable Wideband Digital Receiver

A configurable wideband digital receiver with multiple signal detection capability is presented The implementation of multiple signal detection scheme is often a challenge due to the timing and hardware constraints. The efficient multiple detection scheme presented in this paper employs hardware reuse by effective configuration and detects multiple signals before the next set of buffered data arrives for processing. Performance evaluation of the configurable receiver to detect up to five signals, their maximum attainable instantaneous dynamic range (IDR) and frequency detection error analysis are presented.

Design and performance measurement of a high-performance computing cluster

Graphics processor units (GPU) are specialized hardware accelerators that can be utilized for computations needing high parallelism and high memory bandwidth. Propelled by the attractive Flops/

Design, implementation and evaluation of a brain-computer interface controlled mechanical arm for rehabilitation

ratio and its capability to outperform a CPU cluster at the equivalent cost, large-scale GPU clusters are gaining popularity in the high-performance computing (HPC) community. However, the design challenges associated with the setup and application development process for an efficient HPC cluster includes: a) data movement and locality on the hardware accelerators; b) task mapping and allocation; and c) setting up a well-balanced system. In this paper, we present our experience setting up a GPU cluster for HPC applications; particularly signal processing for digital wideband receivers. We describe the architecture, hardware and software platform of the proposed cluster. The proposed GPU cluster implementing a 1.25 GHz digital wideband receiver was compared and contrasted against a HPC based predecessor receiver system. The adaptability of the GPU cluster was further demonstrated by utilizing it for a multiple receiver implementation that demanded higher data processing capability and throughput.

2.5 GSPS/1 GHz wide band digital receiver

Artificial limbs and exoskeletons have been widely used in a variety of applications, from military to medicine. DARPA primarily focuses on developing exoskeletons to aid ground soldiers in both physical performance skills and survivability. Robotic arms have been used to assist individuals who have lost the ability to perform everyday activities such as walking because of grievous medical injuries. In this paper we present design, implementation and evaluation of a mechanical arm controlled by commercially-off-the-shelf brain-computer interface (BCI) technology. The work examines the viability of incorporating the BCI technology to the control system of an exoskeleton or an artificial limb that serves as a rehabilitative tool for individuals to retrain their muscles. The Emotiv Software suite is used to recognize thought patterns and convert them into digital commands that Matlab interface communicates to an Arduino Uno processor which activates a particular motor to move the mechanical arm. Exhaustive simulations were performed to ascertain the performance of the BCI based system.