Chien-In Henry Chen

Low-Power 4-b 2.5 GSPS Pipelined Flash Analog-to-Digital Converters in 0.13 μm CMOS

This paper presents a 4-b low-power, low-voltage flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H); 2)differential comparator; and 3) differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current-mode dual-array structure to reduce the aperture jitter for high-input signal frequency. The differential comparator eliminates the use of the resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits, which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared with the conventional ROM encoder. The ADC is designed in 130-nm CMOS technology. Fast Fourier transform tests prove proper operation of the ADC sampled at 2.5 GHz for the input signal frequency up to 1 GHz

Design and performance evaluation of a 2.5-GSPS digital receiver

Todays very deep submicron IC technology enables high-performance analog and digital applications to be integrated on a single piece of silicon. For this effort, a design of 2.5 giga-sample per second (GSPS) receiver-on-a-chip (ROC) is presented. For our design, we take advantage of a compensation technique to reduce spurs and improve instantaneous dynamic range. A major goal is to produce a low-cost, small, and lightweight, and low-power ROC. Our design will cover a 1-GHz bandwidth (125 - 1125 MHz), and it will correctly process two simultaneous signals by detecting their frequency, pulsewidth (PW), and time of arrival (TOA). The single or dual signal, spur-free dynamic ranges and two signal instantaneous dynamic ranges of our design are high. The minimum frequency separation of two signals is 10 MHz (one channel width), and the maximum amplitude separation (dynamic range) of two signals is 18 dB with the second signal false alarm less than 1%.

FPGA Frequency Domain Based GPS Coarse Acquisition Processor Using FFT

In this paper we describe the use of the FFT on an FPGA to perform lock on coarse acquisition (C/A) code and carrier frequency in a global positioning system (GPS) receiver. A novel technique of sub-sampling is used in this system to obtain data block sizes that match hardware limitations. The system uses 10 ms of data to perform the lock with 6 ms of processing time and theoretically can operate on signals 20 db below the noise floor

A note to low-power linear feedback shift registers

Low power has emerged as a principal theme in todays electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. A paper by Lowy (1996) is quite interesting in this regard. The author talks of a parallel architecture of linear feedback shift registers (LFSRs) and sequence generators that have a lower power dissipation than that of conventional LFSRs. This paper comments on some design improvements and explores some techniques that would make the LFSRs capable of handling different low-power applications. The advantages of using nonprimitive polynomials with two taps in implementing low-power LFSRs are analyzed in this paper. It is found that if the taps are taken from the last and center of the flip-flops, the number of switch requirements reduces from the order of M+N to the order of N, where N is the length of the shift register and M is the number of taps. This sort of tapping also results in a simpler switch minimization algorithm. With our strategies, it is possible to generate much better sequences from Lowys LFSRs structure. Moreover, power dissipation is constant in our case, independent of the number of stages in the LFSRs. Our simulations show that the percentage of power improvement to conventional serial LFSRs is from 51.65% (N=18) to 68.51% (N=28).

Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection

A 2.56-gigasample-per-second (GSPS) fixed-point fixed-precision dynamic kernel function fast Fourier transform (FFT) with a variable truncation scheme (VTS) is designed for real-time wideband signal detection. Using an Atmel 10-bit analog-to-digital converter (ADC), the two-tone real-time signal detection is verified for a bandwidth of 1.14 GHz with 20-MHz channelization and output throughput rates of 50 ns. The proposed design has an averaged single-signal spurious-free dynamic range (SFDR) of 27.7 dB and the ability to detect a weak input signal at -45 dBm. The overall dynamic range (DR) of the system is 40.6 dB. This is possible for a fixed-precision FFT design due to the embedded VTS to extend the total DR while preserving the instantaneous DR (IDR) relationship. In addition, with an ideal 8-bit ADC, the averaged single-signal SFDR of 32.60 dB and the two-tone signal IDR of 22 dB are achieved. The overall DR is 48.3 dB. The dynamic kernel FFT uses about 57% of the slices available on a Xilinx XC4VSX55 Virtex 4 field-programmable gate array (FPGA). In comparison with alternative implementations based on Xilinx LogicCORE 256-point IP FFT for 8-bit data, the processing time and the overall DR are considerably superior. Additional case studies that applying the windowing function and the Taylor-series-based square root approximation show favorable results utilizing the VTS for real-time data acquisition and signal-enhancement algorithms for computing high-bit-width data while minimizing the hardware.

Graph partitioning for concurrent test scheduling in VLSI circuit

Modem VLSI circuits with extensive built-in self-test (BIST) resources have the problem of long testing time if the testing for the different parts of the circuits are executed successively. Herein, we present a heuristic solution, called Weighted Cluster Partitioning (WCP), to the problem of long testing time for VLSI circuits. Some of the techniques in current use exploit parallelism in testing VLSI circuits, but the computation is quite expensive. Our solution is a more efficient and effective procedure which explores the space of concurrent test schedule and leads to a considerable reduction of testing time by suitable incorporation of BIST in the circuit.

Configurable and Expandable FFT Processor for Wideband Communication

A practical fast Fourier transform (FFT) processor can contain several millions of gates, so effective design techniques usually are required in order to guarantee high-speed products. A look-up table (LUT) methodology is developed and demonstrated on variable length (128-1024 point), variable bit-precision (6-12 b) FFT with uniform bit truncation and optimum bit truncation for wideband digital receiver in radar applications. The FFT processors are designed using a standard 130 nanometer CMOS process and operates down to 120 mV. The required processing time for the non-configurable 12-b 1024-point LUT FFT is 15.78 ns at a clock frequency of 470 MHz. The required time for configurable LUT 12-b 1024-point FFT processing is 61 ns. The configurable LUT FFT processor with short transform lengths can be expandable so that they can be used easily to form new FFT processors with longer transform lengths. The performance comparison of conventional FFT, LUT FFT, and configurable LUT FFT for digital wideband receiver application is discussed.

Built-In Self-Test for Low-Voltage High-Speed Analog-to-Digital Converters

This paper presents a built-in self-test (BIST) architecture for testing high-speed analog-to-digital converters (ADCs) with sampling rates in excess of 1 GHz. A methodology for performing mixed-mode BIST simulations is proposed, along with hardware for performing on-chip BIST. The architecture presented utilizes an on-chip read-only memory and allows for the generation of single-frequency as well as multiple frequency test signals. The issues associated with BIST signal generation for low-voltage ADCs are presented. Simulations revealed that the spurious-free dynamic range of the sinusoidal signal generated from the BIST hardware was 25.28 dB with a frequency of 312.5 MHz and 19.88 dB with a frequency of 416.67 MHz. The proposed 8-b segmented current steering digital-to-analog converter was designed by IBM 130-nm complementary metal-oxide-semiconductor process. The effective chip area is 0.51mm2. The design measurement results show a converter rate of 1.25 GHz, a gain bandwidth of 220 MHz, and a consumption of 28.5 mA for a power dissipation of 39.5 mW.

Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test

A configurable two-dimensional (2-D) LFSR based test generator and an automated synthesis procedure are presented. Without storage of test patterns, a 2-D LFSR based test pattern generator can generate a sequence of precomputed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable faults). The hardware overhead is decreased considerably through configuration. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2-D LSFR can also be adopted in chip-level and system-on-a-chip (SoC) BIST.

VHDL behavioral ATPG and fault simulation of digital systems

Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation is becoming more complex, difficult, and costly. Furthermore, circuit designs are increasingly being developed through the use of powerful VLSI computer-aided design (CAD) synthesis tools which emphasize circuit descriptions using high-level representations of functional behavior, rather than physical architectures and layout. Behavior fault simulation applied to the top functional level models described using a hardware description language offers a very attractive alternative to these problems. A new way to simulate the behavioral fault models using the hardware description language (HDL), such as VHDL, is presented. Tests were generated by carrying out the behavioral fault simulation for a few circuit models. For comparison, a gate-level fault simulation on the equivalent circuit, produced via a synthesis tool, was used. The performance analysis shows that a very small number of test patterns generated by the behavioral automatic test pattern generation (ATPG)/fault simulation system detected around 98 percent of the testable gate-level faults that were detected by random test.