Kirti Gupta

MCML D-Latch Using Triple-Tail Cells: Analysis and Design

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.

A novel active shunt-peaked MCML-based high speed four-bit Ripple-Carry adder

This paper proposes a new active shunt-peaked MOS Current Mode Logic (MCML) based four-bit Ripple-Carry adder (RCA) circuit. The technique of active shunt-peaking offer a way of enhancing the performance of MCML gates for high speed digital system designs. The technique suggests active inductor as load to RCA. The paper presents the analysis and operation of the load. The benefits of the proposed technique is verified by designing and simulating various MCML based RCA circuits using resistive, pMOS and active inductor load. An overall performance evaluation in terms of propagation delay, rise time and fall time and a comparison has been done based in PSPICE using 0.18μιη CMOS technology parameters. For a power supply of 3.3 V and data rate of 2.5 GHz, the simulation results show an improvement of 11 to 36 percent in the values of delay parameters for active shunt-peaked RCA in comparison to other existing MCML loads.

New low-power tristate circuits in positive feedback source-coupled logic

Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 µm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.

A novel DFAL based frequency divider

With the increased interest in low power digital devices operating at low frequencies, the demand for high performance adiabatic logic circuits is on the rise. A frequency divider is extensively used for frequency synthesis in transceivers, and Phase Locked Loops (PLL) circuits. This paper proposes a novel diode free adiabatic logic (DFAL) based frequency divider for low power applications. The proposed circuit eliminates the use of diodes in charging and discharging paths to lower the power consumption and amplitude degradation. The functionality of the proposed circuit is verified and compared with the two-phase clocked adiabatic static CMOS logic (2PASCL) based and conventional CMOS frequency divider. All the simulations are performed in Tanner EDA using 180nm CMOS technology parameters. The simulation result shows that the proposed DFAL frequency divider outperforms the 2PASCL divider.

Bus Implementation Using New Low Power PFSCL Tristate Buffers

This paper proposes new positive feedback source coupled logic (PFSCL) tristate buffers suited to bus applications. The proposed buffers use switch to attain high impedance state and modify the load or the current source section. An interesting consequence of this is overall reduction in the power consumption. The proposed tristate buffers consume half the power compared to the available switch based counterpart. The issues with available PFSCL tristate buffers based bus implementation are identified and benefits of employing the proposed tristate buffer topologies are put forward. SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%.

DFAL based implementation of frequency divider-by-3

Power Dissipation being an important parameter of any electronic systems performance is a major topic of interest for scads of researchers. Frequency divider, a basic building block in ample electronic systems, dissipates a very high power and consumes substantial amount of energy. In this paper a frequency divider-by-3 circuit is implemented using diode free adiabatic logic (DFAL), which surpasses the static CMOS logic based frequency divider-by-3 in terms of power dissipation and power delay product (PDP). The functionality of the implemented circuit is verified through TSPICE simulations in Tanner EDA simulator by using 0.18 micron TSMC technology parameters. For the performance measures, average power dissipation and PDP of the DFAL based divider-by-3 circuit is compared with its static CMOS counterpart. The simulation results of constant load capacitance analysis and constant input frequency analysis confirm the superiority of DFAL based frequency divider-by-3.

Low power D-latch design using MCML tri-state buffers

This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters. The power consumption of the proposed D-latch is compared with the D-latch designed using switched based MCML tri-state buffers which indicate that the proposed low power D-latch is power efficient. The simulation result also proves that the low power D-latch consumes 50% less efficient than the other D-latch.

A novel high speed MCML square root carry select adder for mixed-signal applications

This paper presents a MOS current mode logic (MCML) square root carry select adder (SQ-CSA) which can be used as an alternative to MCML ripple carry adder (RCA) when the number of bits in the input words is large. The proposed 16-bit MCML SQ-CSA has been implemented and simulated in PSPICE using TSMC 180 nm CMOS technology parameters. Its performance has been compared with 16-bit RCAs based on CMOS and MCML styles and 16-bit CMOS SQ-CSA. It is found that the proposed 16-bit MCML SQ-CSA reduces the worst case delay by 67.50% and 72.49% in comparison to the MCML and CMOS based RCAs respectively. Also, the proposed 16-bit MCML SQ-CSA adder results in 26.55% reduction in delay in comparison to CMOS SQ-CSA. In terms of power consumption, the proposed MCML SQ-CSA shows a reduction of 58.97% in comparison to CMOS SQ-CSA.

Performance comparison of MCML and PFSCL gates in 0.18 μm CMOS technology

In this paper, the performance of two popular source coupled logic styles, namely, MOS Current Mode Logic (MCML) and Positive Feedback Source Coupled Logic (PFSCL) is investigated. A number of SPICE simulation runs have been carried out using 0.18 μm CMOS technology parameters. The PFSCL circuit show better results than the MCML circuit in terms of propagation delay and area. The effect of process variations through Monte Carlo simulations however shows lower variations in MCML circuits style.

A new improved current mode logic style with feedback for wireless communication

In this paper, a new logic style named as MOS current mode logic with feedback (MCML-FB) is proposed as an alternative to conventional MOS current mode logic (MCML) for implementing digital circuits in wireless communication systems. The proposed circuit style combines the advantages of conventional MCML and positive feedback to improve the performance of wireless systems. The use of feedback enhances the switching speed of the circuit without increasing its power consumption and also reduces the transistors count. Different MCML-FB based circuits such as XOR, carry and 4-bit ripple carry adder are proposed and simulated in PSPICE using 0.18μm CMOS technology parameters. The simulation results shows that the proposed circuits are faster and have less transistors in comparison to conventional MCML circuits. Monte Carlo simulations has also been conducted for both the logic styles to study the effect of process variations and the results shows that the proposed circuits are more prone to variations than the conventional one.