Kiyohito Mukai

Power-Supply Noise Reduction with Design for Manufacturability

In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1--13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).

CMP dummy pattern insertion with reduction in power supply voltage drops

In recent years it has become apparent that power supply voltage drops during circuit operation can result in abnormal operations in ULSI semiconductor chips. To resolve this problem, we have inserted a decoupling capacitor into our products. This paper presents insertion methods for internal decoupling capacitors to reduce the voltage-drop problem in chemical mechanical polish (CMP) and ultra large-scale integration (ULSI). A decoupling capacitor has a high pattern density leading to high density locally in the domain in which it is placed. Consequently, arranging conventional decoupling capacitors is problematic for CMP and lithography due to insufficient depth of focus (DOF). In this study, we first review and develop estimates for the decoupling capacitor and area fill insertions and propose an imitation dummy pattern comprising decoupling capacitors. We then perform an analysis to determine if there is an effective decrease in voltage drop without diminished yield. Finally, we evaluate the proposed techniques using layout test cases from industry.