Hiroyuki Tsujikawa

Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement

The advances in semiconductor manufacturing, EDA tools, and VLSI design technologies are enabling circuit designs with increasingly higher speed and density. However, this trend is causing the on-chip power distribution network to experience larger dynamic voltage fluctuations due to dynamic voltage drop, L di/dt noise, and/or LC resonance. As a result, the analysis of power-integrity, as well as the evaluation and calibration of the analysis methodology, has become a major challenge in designing high-performance circuits. An innovative vectorless dynamic power-ground noise analysis approach is discussed in this paper. This approach addresses full-chip complexity with transistor-level accuracy. This analysis approach demonstrated very good correlation with an on-chip supply noise measurement in 0.13-/spl mu/m CMOS technology, capable of achieving 100 /spl mu/V/100 ps resolution.

Dynamic power-supply and well noise measurement and analysis for high frequency body-biased circuits

Dynamic noises on power-supply as well as multiple wells necessary for body-biased circuits show frequency components strongly characterized by the interaction of circuit operation and AC transfer of biasing networks. Measurements with the resolution of 100-ps and 100-uV for a few 100-ns and 1-V ranges on multiple points in a product register file are performed at various operating frequencies up to 400 MHz and show the noises clearly emphasized in frequency domain by the interaction. A proposed analysis flow recruiting a fast SPICE simulator and parasitic extractors can predict the dynamic noises due to combined power supply, ground, well, and substrate interactions, and provide robustness to the design of body-bias control circuitry.

Power-Supply Noise Reduction with Design for Manufacturability

In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1--13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).

An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs

A semidynamic timing analysis flow of dynamic drop consideration applicable to a large-scale circuit is proposed. This technique is compared not only with SPICE simulation but with measurements using built-in noise probing and on-chip delay monitoring techniques, which validates the proposed flow.

Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits

Dynamic power supply noise measurements with resolutions of 100 ps and 100μV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias networks AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs

We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.

An EMI-noise analysis on LSI design with impedance estimation

The EMI noise of LSI has become more significant factor for LSI reliability. The result of a transistor-level simulator was not compared sufficiently with measurement and needs the final layout. This paper shows an EMI-noise analysis method at the early stage of the LSI design. The spectrum of the power supply current and the frequency response of the LSI estimated impedance are merged analytically at high speed. The current can be calculated at high speed by a gate level simulator with a triangle model. The experimental results show that our method has a high accuracy that is correlated with measurement results. Furthermore, the estimation method of the LSI impedance enables EMI noise prediction at the early stage of LSI design. The information obtained from our method can also help designers to improve LSI and electronic systems design quality.

CMP dummy pattern insertion with reduction in power supply voltage drops

In recent years it has become apparent that power supply voltage drops during circuit operation can result in abnormal operations in ULSI semiconductor chips. To resolve this problem, we have inserted a decoupling capacitor into our products. This paper presents insertion methods for internal decoupling capacitors to reduce the voltage-drop problem in chemical mechanical polish (CMP) and ultra large-scale integration (ULSI). A decoupling capacitor has a high pattern density leading to high density locally in the domain in which it is placed. Consequently, arranging conventional decoupling capacitors is problematic for CMP and lithography due to insufficient depth of focus (DOF). In this study, we first review and develop estimates for the decoupling capacitor and area fill insertions and propose an imitation dummy pattern comprising decoupling capacitors. We then perform an analysis to determine if there is an effective decrease in voltage drop without diminished yield. Finally, we evaluate the proposed techniques using layout test cases from industry.