Kiyomi Koyama

Computer Aided Design Software for Designing Phase-Shifting Masks

Computer aided design software has been developed in order to improve the efficiency of completing the design of Levenson-type phase-shifting masks. The software assists designers with the functions of automatic shifter arrangement and verification. In addition, to cope with contradictory spots where Levenson-type alternating phase shifting is impossible, the functions of extracting the shapes causing contradiction and of phase assignment with priority are also offered. The principle of shifter arrangement is that when the distance between clear mask areas is less than a certain threshold, a shifter is positioned into one of the clear areas. According to the principle, the number of pairs whose mutual phases have to be opposite decreases. and thus the degree of freedom to arrange shifters increases. The software was developed on a workstation. and its performance was evaluated using several layouts of 64Mbit dynamic random access memory. The average processing time for layouts with 300-400 shapes was about 1 min.

Hierarchical Processing of Levenson-Type Phase Shifter Generation

The hierarchical processing of Levenson-type phase shifter generation has been developed. It is integrated with a computer aided design (CAD) system, which makes modification of conflict spots easy for designers. In order to keep CAD data compressed during phase assignment, phase information is stored as a combination of two properties, phase and group reversal. Phase assignment is generally executed cell-by-cell from the bottom up. In each cell, the region processed is kept to a minimum in order to achieve efficient processing. The intrinsic problem of bottom-up hierarchical processing is the merge problem in which patterns to be merged at the cell boundary have different phases, and it is treated with retry processing. The hierarchical phase assignment was applied to 4M-bit memory with a core circuit and the effectiveness of the hierarchical processing was demonstrated. The processed data were compressed to about 1/20, and processing time was reduced by at least 1/2 of those by flat processing.

Method of Designing Phase-Shifting Masks Utilizing a Compactor

A new method is proposed for designing Levenson-type phase-shifting masks. In this method, phases are assigned in an intermediate layout, and then the intermediate layout is converted to a final layout. In practice, the intermediate layout is a symbolic layout, and the symbolic layout is converted to a mask layout by a compactor. According to the strategy, no conflict spots arise during the operation, which greatly improves design efficiency. This design method is applicable to random patterns in a memory peripheral circuit and in microcomputer chips. As a result of application to the peripheral circuit of dynamic random access memory (DRAM), about 16% shrinkage of the mask area was obtained, compared with a conventional mask. As for a microcomputer chip, 12% shrinkage of mask area was obtained under the condition of 50% shrinkage of aluminum-wire spacing. Together with the interactive method reported before, which is applicable to a memory core circuit, the design of the Levenson-type masks for standard LSIs is totally covered.

Large-Area Optical Proximity Correction with a Combination of Rule-Based and Simulation-Based Methods

We have developed a practical one-dimensional (1D) optical proximity correction (OPC) system based on a combination method. Our OPC system integrates a rule-based and a simulation-based method so that correction time can be reduced to a minimum, while maintaining sufficient accuracy for the correction. The correction accuracy depends on a simulator implemented in the system. By incorporating the 1D context within the range of the proximity effect into the rule table, higher accuracy in the OPC is obtained as compared with conventional methods which involve looking up tables based on duty ratio, or distance to the nearest neighbor. We applied this system to the linewidth correction of 0.3-µm rule logic gates, and obtained width specifications within ±10% and DOF ±0.4 µm. Since correction is basically carried out at the speed of a rule-based correction, our OPC method is applicable to large area layouts. The correction time for a layout of 116 mm2 was only 64.2 min. The results of OPC for real devices such as SRAMs and DRAMs are also given, demonstrating the feasibility of large-area 1D OPC.

Character Projection EB Data Conversion System Combined with Throughput Analyzer

An electron beam (EB) data conversion system for a character projection (CP) writing method has been constructed. The system has been developed based on an EB data conversion system for a variable-shaped beam (VSB), and a formatting module for CP writing was added. In addition, several functions have been developed to analyze CP writing patterns, and combined with the system. The functions aim to select the CP writing patterns that best reduce writing time and to achieve the highest throughput. The new system was applied to a real LSI pattern to test the conversion function and to estimate the conversion speed. A model pattern of a 1 Gbit dynamic random access memory was successfully converted to EB data format. The conversion processing time was less than 14 min for each layer.

Advanced electron-beam writing system EX-11 for next-generation mask fabrication

Toshiba and Toshiba Machine have developed an advanced electron beam writing system EX-11 for next-generation mask fabrication. EX-11 is a 50 kV variable-shaped beam lithography system for manufacturing 4x masks for 0.15 - 0.18 micrometer technology generation. Many breakthroughs were studied and applied to EX-11 to meet future mask-fabrication requirements, such as critical dimension and positioning accuracy. We have verified the accuracy required for 0.15 - 0.18 micrometer generation.

Emission characteristics of dispenser cathodes with a fine-grained tungsten top layer

Abstract In order to improve the emission stability of the Ir-coated dispenser cathode under ion bombardment, a fine-grained tungsten top layer was applied on the substrate porous tungsten plug before Ir coating. The emission characteristics were studied after being assembled in a CRT gun. Cathode current was measured under pulse operation in a range of 0.1–9% duty. Remarkable anti-ion bombardment characteristics were observed over the range of 1–6% duty. The improved cathode showed 1.5 times higher emission current than that of a conventional Ir-coated dispenser cathode at 4% duty. AES analysis showed that the recovering rates of surface Ba and O atoms after ion bombardment were 2.5 times higher. From these results it is confirmed that the Ir coated cathode with a fine-grained tungsten top layer is provided with a good tolerance against the ion bombardment.

Life estimation of Ir-coated dispenser cathodes and heaters for cathode ray tubes

Two types of Ir-coated dispenser cathode for cathode ray tubes (CRTs) have been developed and their practical application has been realized. The heater powers of these cathodes are 1.31 W and 0.76 W. Life tests up to 42,000 h were conducted at two levels of cathode temperature. Based on the emission residual ratio, stability of the Ir layer and the size of ion-bombardment nicks, it was found that the minimum life expectancy was more than 70,000 h. A heater for CRTs is used in conditions where a voltage of about 200 V is normally applied between the heater and the cathode. Therefore, it is important to design such a heater so as to lower the heater temperature and to develop a coating layer with high dielectric strength. In order to solve this problem, a new coating layer has been developed. A life test has been conducted for 39,000 h with a voltage of 300 V applied between the heater and the cathode, at several heater temperature levels. From the results obtained, the minimum life of the newly developed heater is estimated to be more than 80,000 h.

Shape Data Operations for VSB LB Data Conversion Using CAD Tools

For fast electron beam (EB) data conversion, an improved system of hierarchical process has been constructed. Several functions have been added to hierarchically perform shape data operations with increased efficiency. The added functions aim to cut redundant checks in oversizing, to reduce shape data expansion in array data handling and to speed cell overlap checks. These functions were implemented on a computer-aided design (CAD) system utilizing software tools available on it. The new system was applied to the variable shaped beam (VSB) EB data conversion and demonstrated to have better performance. A 16 Kbit SRAM design, conventionally degenerated near a flat level process, was successfully processed in a hierarchical manner, and performance gains of 1.6 to 3.1 were obtained.

Pattern-data preparation method to enhance high-throughput mask fabrication in variable-shaped e-beam writing system

We have developed a new method of preparing pattern data to increase throughput of an EB writing system. The main idea is to expand cells smaller than a threshold size to the corresponding upper level cells during hierarchical shape data operations, which leads to reduction of the number of subfields and shots in our EB writing system. The cell expansions, however, could cause increase in the data volume and data conversion time as a result of destroying the hierarchy of CAD data. Therefore, we have introduced an additional rule, that is, not to expand cell arrays which have more elements than a threshold number. The new data conversion processor, which adopts the above-mentioned cell expansion algorithm, has been applied to a 64Mbit and a 256Mbit DRAM. The new module was applied to three layers, that is, the trench layer, the gate poly layer and metal layer of each DRAM. As a result, we found that the number of subfields and the number of shots were reduced by about 60% and 35%, respectively, for the average of 6 layers. Resulting throughput was evaluated as 1.8 times for the average of 6 layers. Performance change in the conversion processor has been examined in terms of data volume and data conversion time, and is discussed in the paper.