Kiyonori Ohyu

Hot-electron hardened Si-gate MOSFET utilizing F implantation

A technique is presented for incorporating fluorine (F) into the gate-oxide film, and the subsequent improvement of channel-hot-electron hardness of the resulting MOSFET is reported. This technique uses low-energy F implantation onto the surface of the polysilicon gate-electrode, followed by annealing at 950 degrees C to diffuse F into the gate SiO/sub 2/ toward the SiO/sub 2//Si interface. The improved hot-electron hardness is explained by a model involving a strain relaxation near the SiO/sub 2//Si interface by fluorine incorporation that results from Si-F bond formation.<<ETX>>

MeV-ion-induced damage in Si and its annealing

Abstract The interactions between buried defects and impurities formed by MeV ion implantation in Si have been investigated from the following aspects: First, the interactions between the O atoms in CZ Si and the defects introduced during annealing after implantation with various ions, such as B, C, F, Si, P, Ge and As, are discussed by clarifying the amount, nature, morphology and depth distribution of the generated defects. Generally, oxygen atoms are gettered in two different regions of implanted layers. A shallow O peak appears in regions near the surface (between 0.5 and 1.5 μm deep), where no visible defect band exists. A deep peak of O is observed at locations where severe defects exist. These results are explained by considering ion mass, mismatch stress and point defects generated along individual ion tracks. Second, the effect of additional C and F implantation on density reduction and on changes in the configuration of defects formed by individual P and B implantation is reported. Under optimum implantation conditions, an effective suppression of elongated defect formation is observed after annealing at temperatures above 800 ° C. The results are discussed on the basis of interactions between implantation-induced interstitials (which are responsible for secondary defect formation) and implanted C and F atoms.

0.1 mu m CMOS devices using low-impurity-channel transistors (LICT)

Summary form only given. It was found that LICTs are very effective for providing low threshold voltages with good turn-offs in 0.1 mu m CMOS devices. Attention is given to device fabrication criteria, key process technologies used, and the features achieved using LICTs.<<ETX>>

Advantages of Fluorine Introduction in Boron Implanted Shallow p+/n-Junction Formation

The advantages of fluorine introduction on fabrication of shallow p+/n-junctions have been demonstrated. This was done by implanting fluorine onto the boron implanted p+/n-junction area prior to annealing. By introducing optimized amounts of fluorine, (1) the boron redistribution after annealing is suppressed, (2) the concentration of activated boron becomes higher, and (3) the leakage current level of the p+/n-junction decreases. These behaviors may be due to interactions between fluorine and defects in the silicon substrate or at the SiO2/Si interface.

Design and performance of 0.1- mu m CMOS devices using low-impurity-channel transistors (LICT's)

0.1- mu m CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135 mu m, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICTs suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings.<<ETX>>

The origin of variable retention time in DRAM

To investigate the origin of DRAM variable retention time (VRT), we use test structures and carefully measure the time dependence of leakage current in DRAM. Consequently we find for the first time that the junction leakage current fluctuates just like random telegraph signal. We analyze the leakage current fluctuation in detail and find it the origin of VRT

Improvement of SiO2/Si Interface Properties Utilising Fluorine Ion Implantation and Drive-in Diffusion

Thermal drive-in diffusion of ion-implanted F atoms has been employed to fluorinate SiO2/Si interfaces and thereby improve their electrical properties. The interface state density can be lowered with little fixed charge generation. Correspondingly, pn-junction surface leakage current decreases. Furthermore, the interfaces can be hardened against hot-electrons due to Fowler-Nordheim current injection and avalanche current at the junction surface. As a result, a fluorinated MOSFET shows higher hot-carrier immunity. It is pointed out that there is an optimal F dose for these improvements to be achieved.

Radiation hardened micron and submicron MOSFETs containing fluorinated oxides

The generation of interface traps and oxide trapped charge in fluorinated MOSFETs and MOS capacitors has been found to depend strongly on the amount of fluorine introduced. In this study, the fluorine is introduced by low-energy F implantation into the surface layer of the polycrystalline silicon gate electrode, followed by annealing at 950 degrees C to diffuse F into the gate SiO/sub 2/, toward the SiO/sub 2//Si interface The improved interface radiation hardness is attributed to the strain relaxation near the SiO/sub 2//Si interface due to fluorine incorporation. An optimum F implant dose has been found to exist for a given technology; in the present case the optimum dose appears to be 2*10/sup 15/ cm/sup -2/. The results demonstrate the potential of the technique for producing radiation hard micron and submicron MOS devices. >

Channel length and width dependence of hot-carrier hardness in fluorinated MOSFETs

A study of the interface degradation caused by channel-hot-electron (CHE) and substrate-hot-electron (SHE) injection in fluorinated MOSFETs and in unfluorinated control over a wide range of channel lengths and widths is discussed. In all cases, the fluorinated MOSFETs are more resistant to hot-electron-induced interface damage, although the beneficial effect of fluoride becomes less significant for submicrometer devices. For nonfluorinated control devices, a significant gate-size dependence of the transconductance degradation is observed after either CHE or SHE injection. In contrast, the fluorinated devices exhibit almost no gate-length dependence in the range of 0.6-10.0 mu m or gate-width dependence in the range of 1.6-10.0 mu m after SHE injection, in which the injected hot electrons assume much better areal uniformity than in CHE injection. However, significant gate-size dependence was observed in fluorinated devices after CHE injection, primarily due to the spatial nonuniformity of the CHE damage. The beneficial effect of F and its influence on the gate-size dependence in response to SHE injection may be attributed to the local strain relaxation near the SiO/sub 2//Si interface where F is incorporated in the Si-O network. These results also suggest that the development of local-strain relaxed isolation technology will be important for deep-submicrometer MOSFETs.<<ETX>>

A mechanism and a reduction technique for large reverse leakage current in p-n junctions

The origin of anomalously large p-n junction leakage current in Si is investigated. The leakage has strong electric field dependence and weak temperature dependence, and therefore cannot be explained by either generation-recombination current or diffusion current. It may be explained by the local Zener effect at local enhancement of the electric field around small precipitates in the depletion layer. Supposing a spherical precipitate, the electric field will be enhanced as much as 1.3 times for a SiO/sub 2/ precipitate and 3 times for a metal precipitate. The leakage features are explained by the electric field dependence and the temperature dependence of the local Zener probability. A new approach to reduce the local Zener probability by controlling the profile of the electric field is proposed, and the validity of the approach is confirmed by direct experiment and by improvement in the refresh operation of DRAM cells. >