Kensuke Okonogi

The origin of variable retention time in DRAM

To investigate the origin of DRAM variable retention time (VRT), we use test structures and carefully measure the time dependence of leakage current in DRAM. Consequently we find for the first time that the junction leakage current fluctuates just like random telegraph signal. We analyze the leakage current fluctuation in detail and find it the origin of VRT

Single silicon vacancy-oxygen complex defect and variable retention time phenomenon in dynamic random access memories

The variable retention time phenomenon has recently been highlighted as an important issue in dynamic random access memory (DRAM) technology. Based on electrically detected magnetic resonance and simulation studies, we suggest that a single Si vacancy-oxygen complex defect is responsible for this phenomenon, when the defect is embedded in the near surface drain-gate boundary of a DRAM cell.

Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time

This is the first detailed study of data retention characteristics of DRAM with bias ECR-CVD oxide-filled shallow trench isolation (STI). It clarifies the relationship between trench sidewall stress and data retention characteristics. Excessive stress on trench sidewalls causes strain and defect-related leakage current, and it degrades data retention time. Strain and defects are introduced by process conditions like deep trenching, high-temperature densification, and vertically etched trenching in bias ECR-CVD oxide-filled trench case. By eliminating the cause of leakage current, fully operating 0.18 /spl mu/m-rule DRAMs have been manufactured.

Quantitative identification for the physical origin of variable retention time: A vacancy-oxygen complex defect model

We quantitatively examined current high-density DRAMs to identify the physical origin of the so-called variable retention time phenomenon, which is characterized by bistability of the data retention time of a DRAM bit. Experimental and theoretical analyses led us to supporting a vacancy-oxygen complex defect model. On the basis of the model, we achieved significant improvements in the VRT bit rate by introducing three control methods, defect reduction, defect deactivation, and stress reduction processes

Determining the relationship between local lattice strain and slip systems of dislocations around shallow trench isolation by convergent-beam electron diffraction

We clarified the generation of process-induced dislocations around a shallow trench isolation (STI) by using convergent-beam electron diffraction. Comparing the resolved shear strain (RSS) of 12 slip systems, we found that at the trench bottom corner the RSS on slip systems (1 −1 1)[0 1 1] and (1 −1 1)[1 0 −1] was largest in all slip systems. In fact, the dislocations of slip systems (1 −1 1)[0 1 1] and (1 −1 1)[1 0 −1] were observed around the trench bottom corner more often than those of any other slip systems. We also found that the large RSS at the trench bottom corner may be due to the corner shape or the intrinsic stress induced during oxidation. Therefore, to control dislocation around STI, the oxidation-induced stress at the trench bottom corner must be reduced, and the shape of the bottom corner must be controlled.

A wafer bonded SOI structure for intelligent power ICs

A novel isolation structure has been developed for intelligent power ICs based on wafer bonding technology. In this method of isolation, an Si-SiO/sub 2/ coexistent surface is directly bonded to a silicon base wafer, resulting in SiO/sub 2/ films buried in part of the composite substrate. This structure makes it easy to isolate control circuits from power output devices. It enables the monolithic integration of output devices having high-current and high-breakdown voltage capability and CMOS control circuits. The authors describe the details of this technology and its application to an intelligent power IC which needs a breakdown voltage of more than 600 V.<<ETX>>

Improvement of Data Retention Time Property by Reducing Vacancy-Type Defect in DRAM Cell Transistor

As electric equipment for portable spreads through a world widely, development of a low power consumption device is required strongly. DRAM development also has the same demand. Since DRAM needs a long refresh cycle in order to realize low power consumption, improvement of data retention time property is one of the important subjects. Among all the cell transistors in a DRAM chip, a few cells with short retention time, which are called minority bits, exist. Therefore, in order to get a long refresh cycle, it is indispensable to reduce the number of minority bits. The cause of minority bit generation has not been investigated in detail. In last year, however, we clarified one cause of the minority bit generation and proposed a new mechanism of data retention time degradation (Okonogi et al., 2004). Our results showed that the triangular intrinsic stacking faults in depletion layer of minority bits enhance junction leakage current through a trap-assisted tunneling. Since the defect is the aggregate of silicon vacancy at the compressive lattice strain region, the defect growth is suppressed by controlling the lattice strain. But, minority bit did not disappeared completely by this stress control. This result suggests that the small vacancy-type defect, such as point defect, still exists. In the present paper, the cause of the leakage current of a real DRAM cell was analyzed using EDMR (electrically detected magnetic resonance). The small point defect that remains in depletion region of a cell transistor was investigated. Furthermore, since one annealing process that enhances the occurrence of the point defect could be specified, the annealing condition dependence of the defect density was investigated. Consequently, for the first time, relationship between the number of minority bits and the density of point defect was clarified

Lattice strain design in W/WN/poly-Si gate DRAM for improving data retention time

A lattice strain design based on a novel model drastically improves the data retention property of DRAMs fabricated through a polymetal gate (W/WN/Poly-Si) process. We clarified that vacancy-type stacking faults are located along the metallurgical p-n junction at the gate edge in tail-mode bits with respect to data retention time. The origin of the vacancy-type stacking faults appeared to be a combination of residual vacancies induced by ion implantation and the compressive lattice strain generated by STI and gate mechanical stresses. To relax the lattice strain, we carefully controlled the internal stresses in polymetal gate and STI materials. As a result, the data retention time was up to twice that with the conventional process.

Fluorine-vacancy defects in fluorine-implanted silicon studied by electron paramagnetic resonance

An electron paramagnetic resonance (EPR) study on fluorine-vacancy defects (FnVm) in fluorine-implanted silicon is demonstrated. Fluorine implantation is an important technology for Si microdevices and EPR measurements showed that this process created a variety of FnVm defects of different sizes (V2, V4, and V5). In FnVm, a Si–F bond exhibited a different chemical nature compared to a Si–H bond in hydrogen-vacancy complexes. The most primitive defect was FV2 (F0 center) and the final types were FnV5 (F1 center) and FnV2 (F2 center) which increased in annealing processes as low temperature as 200u2009°C.

Void-Free Bonded SOI Substrates for High-Voltage, High-Current Vertical DMOS-Type Power ICs

New isolated structures for intelligent power ICs were developed using a wafer bonding technique. These structures have partial buried oxide films for dielectric isolation and buried poly-Si layers for wafer bonding. In this bonding technique, bonding surfaces are a poly-Si layer and a crystalline silicon surface; this combination of bonding surfaces leads to void-free bonding. The electrical perfection of the vertical output device in the new structure was obtained by diffusing antimony into the poly-Si layer. These results indicate that intelligent power ICs can be manufactured by using the new structure.