Kiyoshi Oguri

Plastic cell architecture: towards reconfigurable computing for general-purpose

We propose a new architectural reference based on programmable logic devices that we call Plastic Cell Architecture (PCA). PCA is a reference for implementing a mechanism of a fully autonomous reconfigurability, which is also introduced in this paper. This reconfigurability is a further step toward general-purpose reconfigurable computing, introducing variable- and programmable-grain parallelism to wired logic computing. The PGA architecture is a fusion of an SRAM-based FPGA and cellular automata, where the cellular automata are dedicated to support the run time activities of the circuits configured on the architecture. PCA computing follows the object-oriented paradigm, in that the circuits are regarded as objects. These objects can be described in a hardware description language that features the semantics of dynamic module instantiation. Following the discussions on our research direction, this paper mainly focuses on the mechanism of autonomous reconfigurability and the PCA architecture.

Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm

In this paper, deep pipelined FPGA implementation of a real-time image-based human detection algorithm is presented. By using binary patterned HOG features, AdaBoost classifiers generated by offline training, and some approximation arithmetic strategies, our architecture can be efficiently fitted on a low-end FPGA without any external memory modules. Empirical evaluation reveals that our system achieves 62.5 fps of the detection throughput, showing 96.6% and 20.7% of the detection rate and the false positive rate, respectively. Moreover, if a highspeed camera device is available, the maximum throughput of 112 fps is expected to be accomplished, which is 7.5 times faster than software implementation.

PCA-1: a fully asynchronous, self-reconfigurable LSI

This paper describes the asynchronous device features of PCA-1, which is the first VLSI to realize the Plastic Cell Architecture (PCA). PCA is an autonomously reconfigurable hardware architecture consisting of a programmable logic layer and a network of built-in facilities. To realize run-time generation and the deletion of circuit objects with variable grain, the circuits on the logic layer are programmed as self-timed circuits using Look-Up Tables (LUTs). The built-in facilities of PCA-1 are also designed as self-timed circuits to enhance scalability and to minimize power consumption. LSI chips are successfully fabricated, and experimental results are mentioned.

Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation

This paper shows stream-oriented FPGA implementation of the machine-learned Features from Accelerated Segment Test (FAST) corner detection, which is used in the parallel tracking and mapping (PTAM) for augmented reality (AR). One of the difficulties of compact hardware implementation of the FAST corner detection is a matching process with a large number of corner patterns. We propose corner pattern compression methods focusing on discriminant division and pattern symmetry for rotation and inversion. This pattern compression enables implementation of the corner pattern matching with a combinational circuit. Our prototype implementation achieves real-time execution performance with 7-9% of available slices of a Virtex-5 FPGA.

Accelerating Collapsed Variational Bayesian Inference for Latent Dirichlet Allocation with Nvidia CUDA Compatible Devices

Next-Generation Applied Intelligence: 22nd International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2009, Tainan, Taiwan, June 24-27, 2009.

Efficient scheduling of rate law functions for ODE-based multimodel biochemical simulation on an FPGA

A reconfigurable biochemical simulator by solving ordinary differential equations has received attention as a personal high speed environment for biochemical researchers. For efficient use of the reconfigurable hardware, static scheduling of high-throughput arithmetic pipeline structures is essential. This paper shows and compares some scheduling alternatives, and analyzes the tradeoffs between performance and hardware amount. Through the evaluation, it is shown that the sharing first scheduling reduces the hardware cost by 33.8% in average, with the up to 11.5% throughput degradation. Effects of sharing of rate law functions are also analyzed.

Deep-pipelined FPGA implementation of ellipse estimation for eye tracking

This paper presents a deep-pipelined FPGA implementation of real-time ellipse estimation for eye tracking. The system is constructed by the Starburst algorithm on a stream-oriented architecture and the RANSAC algorithm without any external memories. In particular, the paper presents comparative results between three different hypothesis generators for the RANSAC algorithm based on Cramers rule, Gauss-Jordan elimination and LU decomposition. Comparison criteria include resource usage, throughput and energy consumption. The result shows that the three implementations have different characteristics and the optimal algorithm needs to be chosen depending on the amount of resources on FPGAs and required performance.

General-Purpose Computer Architecture Based on Fully Programmable Logic

We propose a new general-purpose computer architecture based on programmable logic. It consists of a dual-structured array of cells accommodating a fixed “built-in part” and a freely programmable “plastic part”. We call this composition the “Plastic Cell Architecture” (PCA). The built-in part with its fully connective two-dimensional mesh structure serves as a communication platform based on the cellular automata model. It is responsible for the configuration of the plastic part which implements a sea of logic gates similar to programmable devices (FPGA). The key point of our architecture is dynamic, distributed object instantiation during runtime. An object can encapsulate data and/or behavior and communicates with other objects through a unique type of message passing implemented in hardware. Thus, PCA combines the merits of fine grained, high performance hardware implementation and the dynamic memory allocation capabilities of software.

Dynamic hyperparameter optimization for bayesian topical trend analysis

This paper presents a new Bayesian topical trend analysis. We regard the parameters of topic Dirichlet priors in latent Dirichlet allocation as a function of document timestamps and optimize the parameters by a gradient-based algorithm. Since our method gives similar hyperparameters to the documents having similar timestamps, topic assignment in collapsed Gibbs sampling is affected by timestamp similarities. We compute TFIDF-based document similarities by using a result of collapsed Gibbs sampling and evaluate our proposal by link detection task of Topic Detection and Tracking.

Plastic Cell Architecture: A Dynamically Reconfigurable Hardware-Based Computer

This paper describes a dynamically reconfigurable hardware-based computer called the Plastic Cell Architecture (PCA). PCA consists of dualstructured sea-of-cells that consist of a built-in part and a plastic part. The built-in part forms ‘cellular automata’ while the plastic part looks like an SRAM-based FPGA. We detail the design flow especially how to implement logic onto the processing element. The advantages of PCA, considering VLSI implementation and several application examples, are also described.