Kiyoto Ohta

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 /spl mu/W are achieved.

A 1.8-ns random cycle SRAM-interface High-speed DRAM (SH-RAM) compiler with Data Line Replica Architecture

The SRAM-interface High-speed DRAM (SH-RAM) is an embedded DRAM that can replace almost all embedded SRAMs in SoC fabricated by a 65-nm LSTP embedded DRAM process. This paper describes the SH-RAM compiler that realizes a 1.8-ns random cycle time and a 1.5-ns random access time at 512-Kb macro without area penalty by High-speed Bit Line Operation and Data Line Replica Architecture.