Naoki Kuroda

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 /spl mu/W are achieved.

An 8 ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D/sup 2/ RAM)

Recent multimedia applications and personal computers require enhanced memory systems. 3D-graphics and networking require faster random cycle and lower latency megabit-scale RAMs. However, the random cycle time of conventional DRAM is too slow and embedded SRAM area is too large to integrate high-density RAM on a chip. The fast random cycle low-latency embedded RAM macro reported here uses a dual-port interleaved DRAM architecture (D/sup 2/RAM). D/sup 2/RAM reduces random cycle time from 50 ns (20 MHz) of conventional DRAM to 8 ns (125 MHz) on a test chip with a 0.25 /spl mu/m embedded DRAM process. Key technologies are (1) interleaved open bitline operation with dual-port memory cell architecture, (2) two-stage pipelined circuit operation and (3) write before sensing (WBS).

A 400MHz random-cycle dual-port interleaved DRAM with striped-trench capacitor

We present a 400MHz random-cycle dual-port interleaved 1.5V DRAM macro with fully sense-signal-loss compensating technologies based on noise-element breakdowns, a striped trench capacitor cell and write-before-sensing by a decoded write-bus circuit technique. The IC is implemented in a 0.15 /spl mu/m CMOS logic process.

A 1.8-ns random cycle SRAM-interface High-speed DRAM (SH-RAM) compiler with Data Line Replica Architecture

The SRAM-interface High-speed DRAM (SH-RAM) is an embedded DRAM that can replace almost all embedded SRAMs in SoC fabricated by a 65-nm LSTP embedded DRAM process. This paper describes the SH-RAM compiler that realizes a 1.8-ns random cycle time and a 1.5-ns random access time at 512-Kb macro without area penalty by High-speed Bit Line Operation and Data Line Replica Architecture.

A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D/sup 2/RAM fabricated by a 0.15-/spl mu/m standard CMOS process.