Klaus D. McDonald-Maier

Autonomous Ship Collision Avoidance Navigation Concepts, Technologies and Techniques

This study provides both a spherical understanding about autonomous ship navigation for collision avoidance (CA) and a theoretical background of the reviewed work. Additionally, the human cognitive abilities and the collision avoidance regulations (COLREGs) for ship navigation are examined together with water based collision avoidance algorithms. The requirements for autonomous ship navigation are addressed in conjunction with the factors influencing ship collision avoidance. Humans are able to appreciate these factors and also perform ship navigation at a satisfactory level, but their critical decisions are highly subjective and can lead to error and potentially, to ship collision. The research for autonomous ship navigation may be grouped into the classical and soft computing based categories. Classical techniques are based on mathematical models and algorithms while soft-computing techniques are based on Artificial Intelligence (AI). The areas of AI for autonomous ship collision avoidance are examined in this paper are evolutionary algorithms, fuzzy logic, expert systems, and neural networks (NN), as well as a combination of them (hybrid system).

Debug support strategy for systems-on-chips with multiple processor cores

On-chip program and data tracing is now an essential part of any system level development platform for system-on-chip (SoC). Current debug support solutions are platform specific and incompatible with processors and active peripherals from other sources, restricting effective design reuse. In order to overcome this reuse challenge, this paper defines interfaces to decouple the debug support from processor cores and other active data accessing units. The on-chip debug support infrastructure is also decoupled from each cores debug support and from the trace port or trace memory, using an additional interface. As a result, this decoupling of the debug support infrastructure provides freedom from a specific SoC platform. These interfaces are applied through a reference design modeled using VHDL that is based on a novel low overhead trace message framework. Compared with a leading implementation of a relevant standard, the reference design is 50 percent more compact while providing improvements in trace compression of 8.4 percent for program trace messages and almost 24 percent for data trace messages. This reference design is a multiple core solution that is compatible with most SoC architectures, including those based on emerging network-on-chip architectures.

SiTra: simple transformations in Java

A number of different Model Transformation Frameworks (MTF) are being developed, each of them requiring a user to learn a different language and each possessing its own specific language peculiarities, even if they are based on the QVT standard. To write even a simple transformation, these MTFs require a large amount of learning time. We describe in this paper a minimal, Java based, library that can be used to support the implementation of many practical transformations. Use of this library enables simple transformations to be implemented simply, whilst still providing some support for more complex transformations.

A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL

With the continuing rise in the complexity of embedded systems, there is an emerging need for a higher level modeling environment that facilitates efficient handling of this complexity. The aim here is to produce such a high-level environment using model- driven development (MDD) techniques that map a high-level abstract description of an electronic embedded system into its low-level implementation details. The Unified Modeling Language (UML) is a high-level graphical-based language that is broad enough in scope to model embedded systems hardware circuits. The authors have developed a framework for deriving very high speed integrated circuit hardware description language (VHDL) code from UML state diagrams and defined a set of rules that enable automated generation of synthesizable VHDL code from UML specifications using MDD techniques. By adopting the techniques and tools described in this paper, the design and implementation of complex state-based systems is greatly simplified.

Debug support, calibration and emulation for multiple processor and powertrain control SoCs [automotive applications]

The introduction of complex SoCs with multiple processor cores presents new development challenges, such that development support is now a decisive factor when choosing a system-on-chip (SoC). The presented development support strategy addresses the challenges using both architecture and technology approaches. The multi-core debug support (MCDS) architecture provides flexible triggering using cross triggers and a multiple core break and suspend switch. Temporal trace ordering is guaranteed down to cycle level by on-chip time stamping. The package sized-ICE (PSI) approach is a novel method of including trace buffers, overlay memories, processing resources and communication interfaces without changing device behavior. PSI requires no external emulation box, as the debug host interfaces directly with the SoC using a standard interface.

Boosting Debugging Support for Complex Systems on Chip

Advanced on-chip debug support can help overcome the challenges of developing real-time embedded systems driven by complex SoCs, making development support a decisive selection factor. One novel approach supports the on-time development of high-quality complex systems without greatly increasing the required design and production resources

Implementing associations: UML 2.0 to Java 5

A significant current software engineering problem is the conceptual mismatch between the abstract concept of an association as found in modelling languages such as UML and the lower level expressive facilities available in object-oriented languages such as Java. This paper introduces some code generation patterns that aid the production of Java based implementations from UML models. The work is motivated by a project to construct model driven development tools in support of the construction of embedded systems. This involves the specification and implementation of a number of meta-models (or models of languages). Many current UML oriented tools provide code generation facilities, in particular the generation of object-oriented code from class diagrams. However, many of the more complex aspects of class diagrams, such as qualified associations are not supported. In addition, several concepts introduced in UML version 2.0 are also not supported.The aim of the work presented in this paper is to develop a number of code generation patterns that allow us to support the automatic generation of Java code from UML class diagrams that support these new and complex association concepts. These patterns significantly improve the code generation abilities of UML tools, providing a useful automation facility that bridges the gap between the concept of an association and lower level object-oriented programming languages.

ESPACENET: A Framework of Evolvable and Reconfigurable Sensor Networks for Aerospace–Based Monitoring and Diagnostics

There is an increasing need to develop flexible, reconfigurable, and intelligent multi-spacecraft sensing networks for aerospace-based monitoring and diagnostics. Technical advancements in ad hoc networking, MEMS devices, low-power electronics, adaptive and reconfigurable hardware, micro-spacecraft, and micro-sensors have enabled the design and development of such highly integrated space wireless sensor networks. This paper proposes the framework for an evolvable sensor network architecture, investigated as part of the ESPACENET project, collocated at the University of Edinburgh, Essex, Kent and Surrey. The aim is to design a flexible and intelligent embedded network of reconfigurable piconodes optimised by a hierarchical multi-objective algorithm. Although the project is targeted at aerospace applications, the same intelligent network can be used for many earth bound applications such as environmental and medical diagnostics

An intrusion detection system against malicious attacks on the communication network of driverless cars

Vehicular ad hoc networking (VANET) have become a significant technology in the current years because of the emerging generation of self-driving cars such as Google driverless cars. VANET have more vulnerabilities compared to other networks such as wired networks, because these networks are an autonomous collection of mobile vehicles and there is no fixed security infrastructure, no high dynamic topology and the open wireless medium makes them more vulnerable to attacks. It is important to design new approaches and mechanisms to rise the security these networks and protect them from attacks. In this paper, we design an intrusion detection mechanism for the VANETs using Artificial Neural Networks (ANNs) to detect Denial of Service (DoS) attacks. The main role of IDS is to detect the attack using a data generated from the network behavior such as a trace file. The IDSs use the features extracted from the trace file as auditable data. In this paper, we propose anomaly and misuse detection to detect the malicious attack.

On-Board Vision Processing for Small UAVs: Time to Rethink Strategy

The ultimate research goal for unmanned aerial vehicles (UAVs) is to facilitate autonomy of operation.Research in the last decade has highlighted the potential of vision sensing in this regard. Although vital for accomplishment of missions assigned to any type of unmanned aerial vehicles, vision sensing is more critical for small aerial vehicles due to lack of high precision inertial sensors. In addition, uncertainty of GPS signal in indoor and urban environments calls for more reliance on vision sensing for such small vehicles. With off-line processing does not offer an attractive option in terms of autonomy, these vehicles have been challenging platforms to implement vision processing on-board due to their strict payload capacity and power budget. The strict constraints drive the need for new vision processing architectures for small unmanned aerial vehicles. Recent research has shown encouraging results with FPGA based hardware architectures. This paper reviews the bottle necks involved in implementing vision processing on-board,advocates the potential of hardware based solutions to tackle strict constraints of small unmanned aerial vehicles and finally analyzes feasibility of ASICs, Structured ASICs and FPGAs for use on future systems.