Andrew B. T. Hopkins

Debug support strategy for systems-on-chips with multiple processor cores

On-chip program and data tracing is now an essential part of any system level development platform for system-on-chip (SoC). Current debug support solutions are platform specific and incompatible with processors and active peripherals from other sources, restricting effective design reuse. In order to overcome this reuse challenge, this paper defines interfaces to decouple the debug support from processor cores and other active data accessing units. The on-chip debug support infrastructure is also decoupled from each cores debug support and from the trace port or trace memory, using an additional interface. As a result, this decoupling of the debug support infrastructure provides freedom from a specific SoC platform. These interfaces are applied through a reference design modeled using VHDL that is based on a novel low overhead trace message framework. Compared with a leading implementation of a relevant standard, the reference design is 50 percent more compact while providing improvements in trace compression of 8.4 percent for program trace messages and almost 24 percent for data trace messages. This reference design is a multiple core solution that is compatible with most SoC architectures, including those based on emerging network-on-chip architectures.

Integrating Multi-Modal Circuit Features within an Efficient Encryption System

The problem of the incorporation of pattern features with unusual distributions is well known within pattern recognition systems even if not easily addressed. The problem is more acute when features are derived from characteristics of given integrated electronic circuits. The current paper introduces novel efficient techniques for normalising sets of features which are highly multi-modal in nature, so as to allow them to be incorporated within a single encryption key generation system based primarily on measured hardware characteristics. The utility of the proposed system lies in the observation that the need for data sent to and from remote network nodes to be secure and verified is substantial. Security can be improved by using encryption techniques based on keys, which are based on unique properties of the individual nodes within the network. This will serve both to minimize the need for key storage and sharing as well as to validate the initiator node of a message.

Key Generation for Secure Inter-satellite Communication

This paper addresses issues relating to the generation of secure encryption keys for use in inter-satellite communications operating in a low power environment. It introduces techniques which possess the potential to generate encryption keys based on properties or features directly associated with the actual satellites and thus removing the necessity for key storage. This research investigates constraints associated with ensuring secure inter-satellite communications for satellite constellations. The need for data sent to and from satellites to be secure and verified is substantial. Security can be improved by using encryption techniques based on keys, which are based on unique properties of the individual nodes within the satellite network. This will serve both to minimize the need for key sharing as well as to validate the initiator node of a message.

Instrumentation of Real-Time Embedded Systems for Performance Analysis

To understand the behaviour of a hard real-time embedded system in the presence of highly nondeterministic architectural features requires empirical measurement and analysis of task execution times. This study compares noninvasive measurement techniques with invasive software instrumentation. It shows through experimentation that low overhead measurement functions introduce just over 0.005 percent error, indicating that invasive techniques can reliably measure task execution time whilst achieving highly desirable platform independence

Normalizing Discrete Circuit Features with Statistically Independent values for incorporation within a highly Secure Encryption System

Protecting hardware devices from unwanted software attacks is a current area of major security concern. Coupled with the need to secure and verify data sent to and from such devices, the need to supply systems capable of uniquely identifying and securing hardware devices is considerable and imminent. This paper introduces techniques which possess the potential to generate unique identifying codes for given hardware devices based on measurable quantities or features associated with the given hardware and software configurations executing upon it. The techniques are investigated by considering abstract properties in order to validate primarily the feature normalization techniques employed prior to the code generation phase which allows features with highly variable distributions, and whose component values are independent of each other, to be employed within the code generation system.

Integrating Feature Values for Key Generation in an ICmetric System

This paper investigates the practicalities of combining values derived from measurable features of given integrated electronic circuits in order to derive a robust encryption key, a technique termed ICmetrics. Specifically the paper explores options for the precise techniques required to combine the derived feature values in order to ensure key stability. Key stability is an essential component of any encryption system but this must be combined with a guarantee of key diversity between devices.

Ensuring Secure Healthcare Communications via ICmetric Based Encryption on Unseen Devices

A workable technique for the stable reproduction of an encryption key from measurable characteristics of Integrated Circuits which have not previously been enrolled or introduced to the system is presented. Such a system offers great potential within practical scenarios where rapid integration of new devices is necessary such as may be found within the healthcare environment.

Ensuring data integrity via ICmetrics based security infrastructure

Society has grown to trust and depend on electronic systems. However, rising complexity, reduced time to market and increased commercial pressure contribute to eroding dependability. At the same time the value of data and high social dependence on the now ubiquitous embedded systems that underlie most products and equipment attract malicious exploits. Tampering of electronic systems to compromise their integrity and the security of their stored and transmitted data is a growing problem in todays connected devices. This manuscript describes research relating to a new concept called ICmetrics capable of improving the security of system-on- chip (SoC) based devices and their data by providing a reliable means of identifying each device and verifying the absence of tampering using each devices unique features and properties. Specifically, this manuscript outlines a methodology to extract low level feature values from a SoC via reconfiguration of its existing debug support circuits that were originally intended to aid system-level development and monitoring. This novel approach to feature extraction yields an area saving of over 30% percent compared with dedicated circuits.

Optoelectronic Measurement Interface for System-on-Chip Debug

This paper details some of the problems in current debug support trace interfaces for Systems-on-Chip (SoC) and the expected bandwidth deficiency to come when further integration enables multiple processor cores and active peripherals. A solution is proposed in the form of an opto-electronic interface integrated at the SoC substrate level to provide a high bandwidth, high electromagnetic immunity link between the SoC and a recieving station.

Trace algorithms for deeply integrated complex and hybrid SoCs

Deeply integrated system-on-chips (SoCs) are now the de-facto solution in realizing the hard real-time control systems that underlay todays advanced products, and real-time tracing is the established means of debugging such systems. This manuscript reviews the techniques used by the leading trace solutions and presents empirical measurement results to evaluate their performance so that their suitability for next generation SoCs can be reliably assessed. Its findings are that current solutions are focused mainly on single processor devices and fail to provide sufficient bandwidth for multiple processor SoCs operating at higher peak clock frequencies. To support these new higher performance devices, novel techniques are required that boost performance; the practicality of more radical developments in this area are discussed.