Klaus-Dieter Roeth

Registration measurement capability of VISTEC LMS IPRO4 with focus on small features

The development of the 45-nm node manufacturing process at leading edge mask shops is nearly finished. In order to reach the required registration measurement performance with a precision to tolerance value of P/T=0.25, the measurement error may not exceed 1.2 nm according to ITRS roadmap. This requires the latest generation of registration measurement tools. In addition, the demand for measuring very small features increases - for standard pattern placement measurements, as well as special engineering tasks, e.g., the position measurement of single contact holes. In this work, the error of pattern placement measurement on an LMS IPRO4 is determined using an analysis of variance methodology (ANOVA). In addition we analyze the capability as a function of the critical dimension (CD) of the registration feature. The results are compared to the previous tool generation.

In-depth overlay contribution analysis of a poly-layer reticle

Wafer overlay is one of the key challenges for lithography in semiconductor device manufacturing, this becomes increasingly challenging following the shrinking of the device node. Some of Low k1 techniques, such as Double Exposure add additional burden to the overlay margin because on most critical layers the pattern is created based on exposures of 2 critical masks. Besides impact on overlay performance, any displacement between those two exposures leads to a significant impact on space CD uniformity performance as well. Mask registration is considered a major contributor to within-field wafer overlay. We investigated in-die registration performance on a critical poly-layer reticle in-depth, applying adaptive metrology rules, We used Thin-Plate-Splinefit (TPS) and Fourier analysis techniques for data analysis. Several systematic error components were observed, demonstrating the value of higher sampling to control mask registration performance.

Experimental test results of pattern placement metrology on photomasks with laser illumination source designed to address double patterning lithography challenges

Double Patterning Lithography techniques place significantly greater demand on the requirements for pattern placement accuracy on photomasks. The influence of the pellicle on plate bending is also a factor especially when the pellicle distortions are not repeatable from substrate to substrate. The combination of increased demand for greater accuracy and the influence of pellicle distortions are key factors in the need for high resolution through-pellicle in-die measurements on actual device features. The above requirements triggered development of a new generation registration metrology tool based on in-depth experience with the LMS IPRO4. This paper reports on the initial experimental results of DUV laser illumination on features of various sizes using unique measurement algorithms developed specifically for pattern placement measurements.

Mask contribution to intra-field wafer overlay

Shrinking wafer overlay budgets raise the importance of careful characterization and control of the contributing components, a trend accelerated by multi-patterning immersion lithography [1]. Traditionally, the mask contribution to wafer overlay has been estimated from measurement of a relatively small number of standard targets. There are a number of studies on test masks and standard targets of the impact of mask registration on wafer overlay [2],[3]. In this paper, we show the value of a more comprehensive characterization of mask registration on a product mask, across a wide range of spatial frequencies and patterns. The mask measurements will be used to obtain an accurate model to predict mask contribution to wafer overlay and correct for it.

In-die mask registration for multi-patterning

193nm immersion lithography is the mainstream production technology for the 20nm and 14nm logic nodes. Considering multi-patterning as the technology to solve the very low k1 situation in the resolution equation puts extreme pressure on the intra-field overlay, to which mask registration error is a major error contributor. The International Technology Roadmap for Semiconductors (ITRS) requests a registration error below 4 nm for each mask of a multi-patterning set forming one layer on the wafer. For mask metrology at the 20nm and 14nm logic nodes, maintaining a precision-to-tolerance (P/T) ratio below 0.25 will be very challenging. Mask registration error impacts intra-field wafer overlay directly and has a major impact on wafer yield. We will discuss a solution to support full in-die registration metrology on reticles.

Critical dimension measurements on phase-shift masks using an optical pattern placement metrology tool

A useful extension of the optical mask pattern placement metrology is the measurement of critical dimensions (CD), exploiting the outstanding mechanical resolution and stability of a corresponding mask metrology machine. In particular the CD measurement on phase-shift masks (PSMs) poses a challenge on the optical measurement method. The paper presents measurements and the corresponding computational modeling of the setup with respect to illumination beam path (reflection, transmission), PSM properties and measurement optics for a dedicated edge detection method. Variables have been the focus variation of the edge position and the critical dimension of the pattern. Based on the modeling outcome the alignment and the illumination have been improved and verification measurements have been performed on various machines of the type Vistec LMS IPRO3. The paper presents the measurements, the modeling and the comparison to the practical measurement results for original and improved setup, showing the achievement of the envisaged 2-nm repeatability.

Fast local registration measurements for efficient e-beam writer qualification and correction

Mask data are presented which demonstrate local registration errors that can be correlated to the writing swathes of stateof-the-art e-beam writers and multi-pass strategies, potentially leading to systematic device registration errors versus design of close to 2nm. Furthermore, error signatures for local charging and process effects are indicated by local registration measurements resulting in systematic error, also on the order of 2nm.

New directions in image placement metrology

Wafer overlay requirement for the 32nm HP node for DRAM volume production is targeted at 6.4nm (single exposure) in 2013. Consequently, this is placing a significantly tighter demand on the pattern placement accuracy on photomasks: at or below 3.8nm (3sigma). In case Double Patterning Lithography (DPL) becomes the manufacturing technique for 32nm and 22nm node devices, the pattern placement specification of dependent layers is less than 3nm, according to the ITRS roadmap. In addition to photomask lithography pattern placement instability, the distortion influence of the pellicle on plate bending is also an error contributor especially when the pellicle distortions are not repeatable substrate to substrate. The combination of increased demand for greater accuracy and the influence of pellicle distortions are key factors in the need for high resolution through-pellicle in-die measurements based on actual device features. A new registration metrology tool dedicated for the 32nm HP node and beyond is under beta testing. Actual status and performance data of the beta evaluation system is provided to verify registration metrology capability for DPL reticle manufacturing; to characterize the reticle contribution to total wafer overlay error; and help keep such error within the required tolerances.

Update on next generation metrology tool for DPL reticles

Double Patterning Lithography (DPL) techniques for next generation wafer exposures are placing greater demand on the requirements for pattern placement accuracy on photomasks for three reasons. First, a new source of wafer overlay error results from interactions between the two masks, so the specification for each individual mask must be tightened to compensate. Second, specifications have become so tight that the distortion caused by the pellicle bending the mask has become a significant contributor to the wafer overlay error budget. Pellicle-induced distortions are particularly insidious because they are not repeatable from substrate to substrate. Third, the tightening of overlay specifications demands tighter e-beam pattern placement control throughout the die, regardless of pattern density. This makes measuring actual features in-die instead of registration test structures important. The combination of increased demand for greater pattern placement accuracy, a need to characterize the influence of pellicle distortions, and the requirement to measure actual device features drives the need for a pattern placement metrology system capable of high resolution through-pellicle in-die measurements. Key enablers of this capability include high measurement resolution, a low noise platform and a long working distance objective. This paper reports experimental results on mask features of various sizes using a next-generation pattern placement metrology system designed to meet the strict DPL requirements outlined here.

Advanced mask-to-mask overlay analysis for next generation technology node reticles

Double Patterning Lithography (DPL) for next-generation wafer exposure is placing greater demands on the requirements for pattern placement accuracy on photomasks: the DPL mask pair must now meet the pattern placement specifications that a single mask was required to meet in previous generations. As a result, each mask in the mask pair must individually conform to much tighter mask registration specs. Minimizing all sources of systematic overlay error has become critical. In addition, the mask-to-mask overlay between the two masks comprising the DPL pair must be measured-a methodology shift from the current practice of referencing mask registration error only to design data. Characterizing mask-to-mask overlay error requires the ability to measure pattern placement errors using in-die structures on reticle pairs. Todays analysis methods do not allow for comparison of registration maps based on different site locations. This gap has created a lack of information about the true overlay impact of mask-to-mask registration errors on masks with few or no common features. A new mask-to-mask overlay analysis method is demonstrated that provides new flexibility for mask-to-mask comparison. This new method enables mask manufacturers to meet fab requirements for DPL, and it enables semiconductor manufacturers to verify if overlay deviations are within acceptable limits.