Klaus-Peter Völkmann

GCA: Global Cellular Automata. A Flexible Parallel Model

A model called global cellular automata (GCA) will be introduced. The new model preserves the good features of the cellular automata but overcomes its restrictions. In the GCA the cell state consists of a data field and additional pointers. Via these pointers, each cell has read access to any other cell in the cell field, and the pointers may be changed from generation to generation. Compared to the cellular automata the neighbourhood is dynamic and differs from cell to cell. For many applications parallel algorithms can be found straight forward and can directly be mapped on this model. As the model is also massive parallel in a simple way, it can efficiently be supported by hardware.

GCA: a massively parallel model

We have previously introduced the massively parallel global cellular automata (GCA) model. Parallel algorithms derived from applications can be mapped straightforward onto this model. In this model a cell in the cell field is dynamically connected (access pattern, dynamic neighbourhood) to other cells. The model can be implemented by pointers stored in the cell state. Via these pointers, each cell has read access to any other cell in the cell field, and the pointers may be changed from generation to generation. We have investigated different types of the model in order of minimize hardware/software implementation cost. So we have classified the GCA into types with respect to space, time or data dependency of the access pattern. We have investigated a number of different GCA algorithms and found out, that in most cases a time dependent access pattern is sufficient. To find out the usefulness of the data dependent access pattern we constructed a sophisticated merge sort algorithm, in which the target addresses are computed in contrast to classical algorithms where the data elements are moved. It turned out, that we could not achieve a speed up which we expected compared to an algorithm implemented on the more simple time dependent model. This is another confirmation that it is sufficient to implement only the time and space dependent model and thus reduce the hardware/software implementation cost.

A Stream Processor Architecture Based on the Configurable CEPRA-S

Stream processing is a very efficient method to process large amounts of data. In contrast to vector architectures, stream processing involves instruction stream which are associated with data streams instead of a single instruction operating on data streams (vectors) thus facilitating individual processing of stream elements. Furthermore, operators in the arithmetic/logic unit can be configured to meet special processing requirements of an application. In the following article an architecture which can be configured as a stream processor is described.

The Cellular Processor Architecture CEPRA-1X and Its Configuration by CDL

The configurable coprocessor CEPRA-1X was developed as a PC plug-in card in order to speed up cellular processing significantly. Cellular Processing is an attractive and simple massive parallel processing model. To increase its general acceptance and usability it must be supported by a software environment, an efficient simulator and a special language. For this purpose the cellular description language CDL was defined and implemented. With CDL complex cellular algorithms can be described in a concise and readable form. A CDL program can automatically be transformed into a logical design for the CEPRA-1X. The design is loaded into field programmable gate arrays for the computation of the state transition of the cells. For time dependent or complex rules the design may be reconfigured between consecutive generations. An example is presented to show the generation of logic code.

Hardware Support for 3D Cellular Processing

Cellular Processing, especially in the 3D realtime case, needs high computing performance. With a special designed coprocessor the requirements can be fulfilled at relatively low cost. First the architectural principles are described which can be used in designing such coprocessors. Second a 3D architecture is presented based on the principles parallel access window, shifting and pipelining. The implementation uses two Field Programmable Logic Arrays thereby performing 66 million of 3D celloperations per second.

Hardware Supported Simulation System for Graph Based and 3D Cellular Processing

This paper presents results of a project in which a hardware supported simulation system for Cellular Processing (CP) is implemented. For three dimensional regular CP the hardware archltecture, the cellular description language CDL and a method for the efficient generation of the simulator kernel are explained. For irregular graph based CP the principal characteristics and their hardware support are discussed.