Christian Hochberger

The AMIDAR Class of Reconfigurable Processors

In this contribution we present a novel general model for adaptive processors. We describe its basic principle of operation and introduce several formal characterizations. The adaptive operations that are possible with this model are thoroughly discussed. The model allows runtime variations of the type and number of functional units as well as variations of the communication structure. We introduce simple heuristics to achieve adaptivity of the architecture. Experimental results show that a processor implementing this model can adapt its architecture to the requirements of diverse applications.

Runtime verification for multicore SoC with high-quality trace data

Multicore System-on-Chip (SoC) implementations of embedded systems are becoming very popular. In these systems it is possible to spread out computations over many cores. On one hand this leads to better energy efficiency if clock frequencies and core voltages are reduced. On the other hand this delivers very high performance to the software developer and thus enables complex software systems to be implemented. Unfortunately, debugging and validation of these systems becomes extremely difficult. Various technological approaches try to solve this dilemma. In this contribution we will show a new approach to observe multi-core SoCs and make their internal operations visible to external analysis tools. Also, we show that runtime verification can be employed to analyze and validate these internal operations while the system operates in its normal environment. The combination of these two approaches delivers unprecedented options to the developer to understand and verify system behavior even in complex multicore SoCs.

A resource optimized Processor Core for FPGA based SoCs

Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. Typically, the term configurable system on a chip (CSoC) is used for this kind of usage. A key component in such a CSoC is the processor core. Currently, several cores are available for FPGAs. 32 bit processors like MicroBlaze, NIOS 2 or OpenRisc require a lot of resources, whereas very small solutions like PicoBlaze or Lattice Mico8 are not capable of running reasonably complex software. Thus, there is a gap between these two extremes, which we want to fill with our development SpartanMC. This contribution describes its design objectives, architecture, tools, peripherals and compares it to other well known processor cores.

Hardware based online profiling in AMIDAR processors

Dynamically reconfigurable architectures offer the opportunity to migrate software into hardware functional units at runtime. Architectures derived from the AMIDAR model exhibit such possibilities. Yet, the question has to be answered, which parts of the running application should be transformed into hardware. The migration of complete methods or procedures into hardware is often not feasible. In this contribution we show a hardware circuit that enables the processor to collect an execution profile of Java methods with a high resolution. We also show, how this profile information can be used to make reasonable choices for candidate instruction sequences.

Architecture of Computing Systems – ARCS 2008

Invited Program.- Keynote: Grand Challenges of Computer Engineering.- Keynote: The Impact of Operating Systems on Modern CPU Designs (and Vice Versa).- I Hardware Design.- System Level Simulation of Autonomic SoCs with TAPES.- Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks.- Design of Gate Array Circuits Using Evolutionary Algorithms.- II Pervasive Computing.- Direct Backtracking: An Advanced Adaptation Algorithm for Pervasive Applications.- Intelligent Vehicle Handling: Steering and Body Postures While Cornering.- III Network Processors and Memory Management.- A Hardware Packet Re-Sequencer Unit for Network Processors.- Self-aware Memory: Managing Distributed Memory in an Autonomous Multi-master Environment.- IV Reconfigurable Hardware.- Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks.- Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication.- A Novel Routing Architecture for Field-Programmable Gate-Arrays.- V Real-Time Architectures.- A Predictable Simultaneous Multithreading Scheme for Hard Real-Time.- Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation.- A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA.- VI Organic Computing.- A Reference Architecture for Self-organizing Service-Oriented Computing.- Towards Self-organising Smart Camera Systems.- Using Organic Computing to Control Bunching Effects.- VII Computer Architecture.- A Generic Network Interface Architecture for a Networked Processor Array (NePA).- Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses.- Potentials of Branch Predictors: From Entropy Viewpoints.

A resource optimized SoC Kit for FPGAs

Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. A key component of such configurable system on a chip (CSoC) is the processor core. Available and usable cores are either 32 or 8 bit wide. Thus, there is a gap between these two extremes, which we want to fill with our SoC kit. In this contribution we elaborate on our SoC kit and its components and compare it to other SoC design environments.

On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices

Reconfigurable devices like Configurable Systems on a Chip (CSoCs) have the ability to exchange parts of hardware during runtime. Multimedia applications often require computing power and often can be accelerated by specific hardware circuits. In this contribution we present the effect of hardware acceleration in reconfigurable devices. We introduce a new model of adaptive processors and describe its basic principle of operation. The model allows runtime variations of the type and number of functional units (including application specific FUs) as well as variations of the communication structure. Then, we discuss our multimedia kernel Inverse Discrete Cosine Transformation (IDCT) and the ability of shifting different parts of the IDCT into hardware. Simulation results show that hardware acceleration of multimedia operations in an adaptive processor leads to significant performance gains and therefore reduces energy consumption.

Still Image Processing on Coarse-Grained Reconfigurable Array Architectures

Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recently coarse-grained reconfigurable array architectures (CGRAs), such as the ADRES CGRA and its corresponding DRESC compiler are gaining more popularity due to several technological breakthroughs in this area. We investigate the mapping of two image processing algorithms, Wavelet encoding and decoding, and TIFF compression on this novel type of array architectures in a systematic way. The results of our experiments show that CGRAs based on ADRES and its DRESC compiler technology deliver improved performance levels for these two benchmark applications when compared to results obtained on a state-of-the-art commercial DSP platform, the c64x DSP from Texas Instruments. ADRES/DRESC can beat its performance by at least 50% in cycle count and the power consumption even drops to 10% of the published numbers of the c64x DSP.

CDL++ for the Description of Moving Objects in Cellular Automata

We introduce a new model for objects which can move around on a cellular grid. The model consists of two phases, the movement phase and the conflict resolution phase. In the movement part of the description objects specify their desired direction. The conflict, which occurs when alternative objects want to move to the same free cell, is resolved in the conflict resolution part. The cellular description language CDL was extended to CDL++ in order to describe moving objects. This extension is automatically converted into a two-phased CDL program.

Solving Routing Problems with Cellular Automata

New variants of the classical Lee algorithm for the routing of connections on printed circuits or chips have been found when mapping it onto the cellular processing model. Two cellular algorithms are described: (1) a cellular shortest path algorithm with only 14 states per cell, which is independent of the grid size and (2) a parallel algorithm for routing multiple nets simultaneously.