Knut Åkesson

Supremica - An integrated environment for verification, synthesis and simulation of discrete event systems

An integrated environment, Supremica, for verification, synthesis and simulation of discrete event systems is presented. The basic model in Supremica is finite automata where the transitions have an associated event together with a guard condition and an action function that updates automata variables. Supremica uses two main approaches to handle large state-spaces. The first approach exploits modularity in order to divide the original problem into many smaller problems that together solve the original problem. The second approach uses an efficient data structure, a binary decision diagram, to symbolically represent the reachable states. Models in Supremica may be simulated in the environment. It is also possible to generate code that implements the behavior of the model using both the IEC 61131 and the IEC 61499 standard

Modeling of discrete event systems using finite automata with variables

To get industrial acceptance of supervisory control theory, there is a need to bridge the gap between the signal-based industrial reality and the event-based supervisory control framework. This paper tries to do this by introducing a modeling formalism with automata extended with variables, guard expressions and action functions. The formalism is suitable for modeling plants and specifications in the supervisory control framework. An algorithm that transforms a set of extended automata into a set of ordinary automata with equivalent behavior, is presented. This allows the user to model complex behaviors with a compact representation, and at the same time use existing algorithms for analysis.

EXPLOITING MODULARITY FOR SYNTHESIS AND VERIFICATION OF SUPERVISORS

Abstract Efficient algorithms for synthesis and verification of supervisors in the Supervisory Control Theory framework are presented. The presented algorithms solve the controllability problem. In many real-world applications both the plant and specification is given as a set of interacting automata or processes. In this work, we exploit this modular structure to reduce the computational effort. First, we present an algorithm that verifies if a given supervisor is controllable with respect to a plant. Second, we show how to synthesize a set of modular supervisors that while interacting with the original supervisors guarantees that the closed system is controllable. Third, we show how the verification algorithm can be used as an efficient language inclusion algorithm. The presented algorithms are benchmarked on a real-world application.

Formal Modeling of Function Block Applications Running in IEC 61499 Execution Runtime

The execution model in a new standard for distributed control systems, IEC 61499, is analyzed. It is shown how the same standard compliant application running in two different standard compliant runtime environments may result in completely different behaviors. Thus, to achieve true portability of applications between multiple standard compliant runtime environments a more detailed execution model is necessary. In this paper a new runtime environment, Fuber, is presented along with a formal execution model. In this case the execution model is given as a set of interacting state machines which makes it straightforward to analyze the behavior of the application and runtime together using existing tools for formal verification.

Sequence Planning for Integrated Product, Process and Automation Design

In order to obtain a unified information flow from early product design to final production, an integrated framework for product, process and automation design is presented. The framework is based on sequences of operations and includes a formal relation between product properties and process operations. This relation includes liaisons (interfaces) and precedence relations, where the precedence relations generate preconditions for the related process operations. From this information a set of sequences of operations (SOPs) is generated. A formal graphical language for hierarchical operations and SOPs is then introduced and defined based on automata extended with variables. Since the operations are self-contained they can be grouped and viewed from different angles, e.g., from a product or a resource perspective. These multiple views increase the interoperability between different engineering disciplines. A case study is performed on a car manufacturing cell, where the suggested modeling framework is shown to give comprehensible SOPs.

Compositional Synthesis of Maximally Permissive Supervisors Using Supervision Equivalence

This paper presents a general framework for efficient synthesis of supervisors for discrete event systems. The approach is based on compositional minimisation, using concepts of process equivalence. In this context, a large number of ways are suggested how a finite-state automaton can be simplified such that the results of supervisor synthesis are preserved. The proposed approach yields a compact representation of a least restrictive supervisor that ensures controllability and nonblocking. The method is demonstrated on a simple manufacturing example to significantly reduce the number of states constructed for supervisor synthesis.

On Formal Analysis of IEC 61499 Applications, Part A: Modeling

IEC 61499 is a standard architecture, based on function blocks, for developing distributed control and measurement applications. However, the standard has no formal semantics and different interpretations of the standard have emerged. As a consequence, it is harder to transfer applications between different standard compliant platforms. This paper presents a formal framework for mathematical modeling and comparison of different execution semantics. The framework provides definitions that allow modeling of applications and execution semantics separately. Together, the models can be used to analyze and compare how an application would behave when executed using different execution semantics. In addition, a mathematical model made possible by the framework has been used as a basis for implementation of a runtime environment that can execute applications and a software tool that generates formal models suitable for formal verification, both assuming different execution semantics.

A BDD-Based Approach for Modeling Plant and Supervisor by Extended Finite Automata

In this paper, we settle some problems that are encountered when modeling and synthesizing complex industrial systems by the supervisory control theory. First, modeling such huge systems with explicit state-transition models typically results in an intractable model. An alternative modeling approach is to use extended finite automata (EFAs), which is an augmentation of ordinary automata with variables. The main advantage of utilizing EFAs for modeling is that more compact models are obtained. The second problem concerns the ease to understand and implement the supervisor. To handle this problem, we represent the supervisor in a modular manner by extending the original EFAs by compact conditional expressions. This will provide a framework for the users where they can both model their system and obtain the supervisor in form of EFAs. In order to be able to handle complex systems efficiently, the models are symbolically represented by binary decision diagrams (BDDs). All computations that are performed in this framework are based on BDD operations. The framework has been implemented in a supervisory control tool and applied to industrially relevant benchmark problems.

Symbolic Computation of Reduced Guards in Supervisory Control

In the supervisory control theory, a supervisor is generated based on given plant and specification models. The supervisor restricts the plant in order to fulfill the specifications. A problem that is typically encountered in industrial applications is that the resulting supervisor is not easily comprehensible for the users. To tackle this problem, we introduce an efficient method to characterize a supervisor by tractable logic conditions, referred to as guards, generated from the models. The guards express under which conditions an event is allowed to occur to fulfill the specifications. To obtain tractable guard expressions, we reduce them by exploiting the structure of the given models. In order to be able to handle complex systems efficiently, the models are symbolically represented by binary decision diagrams and all computations are performed on these data structures. The algorithms have been implemented in a supervisory control tool and applied to an industrially relevant example.

Extraction and representation of a supervisor using guards in extended finite automata

In supervisory control theory, an issue that often arises in real industrial applications is the huge number of states for the supervisor, which requires a lot of memory. Another problem that is typically encountered for the users of supervisory synthesis tools is lack of information and unreadability of the supervisor. In this paper, we introduce a method to characterize a controllable and non-blocking supervisor directly on the modular automata (sub-plants and sub-specifications), by extracting some guard conditions from the synthesized supervisor and the synchronized automaton. Thus, the presented approach may potentially model a complex supervisor using a compact representation whilst not infringe the original modular structure. Furthermore, the guard conditions, which are generated from a set of states, may give the user of the synthesis procedure a better understanding of which states that were removed during the synthesis. In order to obtain more compact guard expressions, we include some unnecessary states (unreachable and extended forbidden states) in the set of states that will be used for guard generation. By exploiting this extra information, it is possible to reduce the logical expressions to more compact guard conditions.