Martin Fabian

Supremica - An integrated environment for verification, synthesis and simulation of discrete event systems

An integrated environment, Supremica, for verification, synthesis and simulation of discrete event systems is presented. The basic model in Supremica is finite automata where the transitions have an associated event together with a guard condition and an action function that updates automata variables. Supremica uses two main approaches to handle large state-spaces. The first approach exploits modularity in order to divide the original problem into many smaller problems that together solve the original problem. The second approach uses an efficient data structure, a binary decision diagram, to symbolically represent the reachable states. Models in Supremica may be simulated in the environment. It is also possible to generate code that implements the behavior of the model using both the IEC 61131 and the IEC 61499 standard

PLC-based implementation of supervisory control for discrete event systems

The supervisory control theory is a general theory for automatic synthesis of controllers (supervisors) for discrete event systems, given a plant model and a specification for the controlled behavior. Though the theory has for over a decade received substantial attention in academics, still very few industrial applications exist. The main reason for this seems to be a discrepancy between the abstract supervisor and its physical implementation. This is specifically noticeable when the implementation is supposed to be based on programmable logic controllers (PLCs), as is the case with many manufacturing systems. The asynchronous event-driven nature of the supervisor is not straightforwardly implemented in the synchronous signal-based PLC. We point out the main problems of supervisor implementation on a PLC, and suggest procedures to alleviate the problems.

Modeling of discrete event systems using finite automata with variables

To get industrial acceptance of supervisory control theory, there is a need to bridge the gap between the signal-based industrial reality and the event-based supervisory control framework. This paper tries to do this by introducing a modeling formalism with automata extended with variables, guard expressions and action functions. The formalism is suitable for modeling plants and specifications in the supervisory control framework. An algorithm that transforms a set of extended automata into a set of ordinary automata with equivalent behavior, is presented. This allows the user to model complex behaviors with a compact representation, and at the same time use existing algorithms for analysis.

EXPLOITING MODULARITY FOR SYNTHESIS AND VERIFICATION OF SUPERVISORS

Abstract Efficient algorithms for synthesis and verification of supervisors in the Supervisory Control Theory framework are presented. The presented algorithms solve the controllability problem. In many real-world applications both the plant and specification is given as a set of interacting automata or processes. In this work, we exploit this modular structure to reduce the computational effort. First, we present an algorithm that verifies if a given supervisor is controllable with respect to a plant. Second, we show how to synthesize a set of modular supervisors that while interacting with the original supervisors guarantees that the closed system is controllable. Third, we show how the verification algorithm can be used as an efficient language inclusion algorithm. The presented algorithms are benchmarked on a real-world application.

Sequence Planning for Integrated Product, Process and Automation Design

In order to obtain a unified information flow from early product design to final production, an integrated framework for product, process and automation design is presented. The framework is based on sequences of operations and includes a formal relation between product properties and process operations. This relation includes liaisons (interfaces) and precedence relations, where the precedence relations generate preconditions for the related process operations. From this information a set of sequences of operations (SOPs) is generated. A formal graphical language for hierarchical operations and SOPs is then introduced and defined based on automata extended with variables. Since the operations are self-contained they can be grouped and viewed from different angles, e.g., from a product or a resource perspective. These multiple views increase the interoperability between different engineering disciplines. A case study is performed on a car manufacturing cell, where the suggested modeling framework is shown to give comprehensible SOPs.

Compositional Synthesis of Maximally Permissive Supervisors Using Supervision Equivalence

This paper presents a general framework for efficient synthesis of supervisors for discrete event systems. The approach is based on compositional minimisation, using concepts of process equivalence. In this context, a large number of ways are suggested how a finite-state automaton can be simplified such that the results of supervisor synthesis are preserved. The proposed approach yields a compact representation of a least restrictive supervisor that ensures controllability and nonblocking. The method is demonstrated on a simple manufacturing example to significantly reduce the number of states constructed for supervisor synthesis.

Efficient supervisory synthesis of large systems

Due to the state-space explosion, many synthesis and verification problems for discrete event systems cannot be solved using traditional state-space traversal algorithms. This work presents efficient methods for reachability search based on symbolic computations using Binary Decision Diagrams. In addition, simple guidelines and quantities for separating hard and easy reachability problems are presented. Furthermore, the performance of the presented algorithms and heuristics is demonstrated on a set of industrial benchmark examples. It is also shown that such examples are much more challenging than some well-known handmade benchmark models. This is also indicated by the presented hardness quantities.

On non-deterministic supervisory control

Supervisory control theory (SCT) is examined in a non-deterministic setting. We show that language controllability of a supervisor is not necessarily equivalent to state controllability when the supervisor is non-deterministic. We give necessary and sufficient conditions for when equivalence holds. The input/output interpretation of the SCT is also examined in a non-deterministic setting. It is known that for a supervisor to act as a controller generating commands for the plant, the supervisor has to be inverse state controllable. We give sufficient conditions for when inverse state controllability is equivalent to inverse language controllability. In systems with concurrently competing production sequences, such as flexible manufacturing systems and multi-purpose batch plants, the specification typically becomes non-deterministic where several products compete for the same production resource. However, unless the plant is only partially observable, it is normally modeled as a deterministic discrete event process. We give necessary and sufficient conditions for the existence of a (possibly) non-deterministic supervisor in this special case.

Towards a Truly Flexible Manufacturing System

Abstract This paper describes the concepts that must be considered in order to achieve a flexible manufacturing system that allows the introduction of new products and new resources without an extensive reprogramming of the control system. In contrast to most other approaches a bottom-up design is attempted. A control software structure based on generic resource models and the basic structure of a resource capability model are presented. A description of how to manufacture the products is also essential. Basic guidelines for a product model are given. Control algorithm aspects are discussed. Operator interface and system dependability are given consideration. Finally, a machining cell, used as a case study, is described.

Solving two supervisory control benchmark problems using Supremica

Two supervisory control benchmark problems for WODESpsila08 are solved using the tool Supremica. Supremica is a tool for formal synthesis of discrete-event control functions based on discrete event models of the uncontrolled plant and specifications of the desired closed-loop behavior. By using formal synthesis of control functions the need for formal verification is reduced since the control functions are computed to automatically fulfill the given specifications, that is, they are ldquocorrect by constructionrdquo. The modeling framework in Supremica is based on finite automata. Supremica implements several techniques for being able to solve large scale problems. In this paper it is evaluated how the algorithms implemented in Supremica that are based on binary decision diagrams performs on the two benchmark problems. The two benchmark problems are generalization of two classical problems; cat and mouse, and the dining philosopherspsila problem. The benchmark problems are parameterized such that it is possible to create problem instances with huge state-spaces. The benchmark shows that supremica can efficiently solve rather large problem instances.